upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.2 KiB
59 lines
1.2 KiB
/*
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* (C) Copyright 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/wdt.h>
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#include <linux/err.h>
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void wdt_stop(struct ast_wdt *wdt)
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{
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clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
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}
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void wdt_start(struct ast_wdt *wdt, u32 timeout)
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{
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writel(timeout, &wdt->counter_reload_val);
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writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
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/*
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* Setting CLK1MHZ bit is just for compatibility with ast2400 part.
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* On ast2500 watchdog timer clock is fixed at 1MHz and the bit is
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* read-only
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*/
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setbits_le32(&wdt->ctrl,
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WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
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}
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struct ast_wdt *ast_get_wdt(u8 wdt_number)
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{
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if (wdt_number > CONFIG_WDT_NUM - 1)
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return ERR_PTR(-EINVAL);
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return (struct ast_wdt *)(WDT_BASE +
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sizeof(struct ast_wdt) * wdt_number);
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}
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int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
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{
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#ifdef CONFIG_ASPEED_AST2500
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if (!mask)
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return -EINVAL;
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writel(mask, &wdt->reset_mask);
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clrbits_le32(&wdt->ctrl,
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WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT);
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wdt_start(wdt, 1);
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/* Wait for WDT to reset */
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while (readl(&wdt->ctrl) & WDT_CTRL_EN)
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;
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wdt_stop(wdt);
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return 0;
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#else
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return -EINVAL;
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#endif
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}
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