upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Lokesh Vutla 802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value ... The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>		10 years ago
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Kconfig	…
MAINTAINERS	…
Makefile	…
board.c	ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value	10 years ago
mux_data.h	…