upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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358 lines
9.2 KiB
358 lines
9.2 KiB
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/uart.h>
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#include "board.h"
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#ifdef CONFIG_TEGRA2_MMC
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#include <mmc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const struct tegra2_sysinfo sysinfo = {
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CONFIG_TEGRA2_BOARD_STRING
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};
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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/* Initialize periph clocks */
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clock_init();
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/* Initialize periph pinmuxes */
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pinmux_init();
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/* Initialize periph GPIOs */
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gpio_init();
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/* Init UART, scratch regs, and start CPU */
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tegra2_start();
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return 0;
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}
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#endif /* EARLY_INIT */
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/*
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* Routine: timer_init
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* Description: init the timestamp and lastinc value
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*/
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int timer_init(void)
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{
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return 0;
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}
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/*
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* Routine: clock_init_uart
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* Description: init the PLL and clock for the UART(s)
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*/
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static void clock_init_uart(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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reg = readl(&clkrst->crc_pllp_base);
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if (!(reg & PLL_BASE_OVRRIDE)) {
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/* Override pllp setup for 216MHz operation. */
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reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
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reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
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writel(reg, &clkrst->crc_pllp_base);
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reg |= PLL_ENABLE;
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writel(reg, &clkrst->crc_pllp_base);
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reg &= ~PLL_BYPASS;
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writel(reg, &clkrst->crc_pllp_base);
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}
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/* Now do the UART reset/clock enable */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
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/* Assert Reset to UART */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_l);
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/* Enable clk to UART */
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reg = readl(&clkrst->crc_clk_out_enb_l);
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reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_l);
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/* Enable pllp_out0 to UART */
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reg = readl(&clkrst->crc_clk_src_uarta);
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reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
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writel(reg, &clkrst->crc_clk_src_uarta);
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/* wait for 2us */
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udelay(2);
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/* De-assert reset to UART */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_l);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
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/* Assert Reset to UART */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_u);
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/* Enable clk to UART */
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reg = readl(&clkrst->crc_clk_out_enb_u);
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reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_u);
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/* Enable pllp_out0 to UART */
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reg = readl(&clkrst->crc_clk_src_uartd);
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reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
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writel(reg, &clkrst->crc_clk_src_uartd);
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/* wait for 2us */
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udelay(2);
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/* De-assert reset to UART */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_u);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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}
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/*
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* Routine: pin_mux_uart
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* Description: setup the pin muxes/tristate values for the UART(s)
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*/
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static void pin_mux_uart(void)
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 reg;
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#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
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reg = readl(&pmt->pmt_ctl_c);
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reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
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writel(reg, &pmt->pmt_ctl_c);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */
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reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
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reg = readl(&pmt->pmt_ctl_b);
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reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
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writel(reg, &pmt->pmt_ctl_b);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_GMC; /* Z_GMC = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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}
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/*
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* Routine: clock_init_mmc
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* Description: init the PLL and clocks for the SDMMC controllers
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*/
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static void clock_init_mmc(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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/* Do the SDMMC resets/clock enables */
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/* Assert Reset to SDMMC4 */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_l);
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/* Enable clk to SDMMC4 */
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reg = readl(&clkrst->crc_clk_out_enb_l);
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reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_l);
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/* Enable pllp_out0 to SDMMC4 */
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reg = readl(&clkrst->crc_clk_src_sdmmc4);
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reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
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reg |= (10 << 1); /* n-1, 11-1 shl 1 */
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writel(reg, &clkrst->crc_clk_src_sdmmc4);
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/*
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* As per the Tegra2 TRM, section 5.3.4:
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* 'Wait 2 us for the clock to flush through the pipe/logic'
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*/
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udelay(2);
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/* De-assert reset to SDMMC4 */
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reg = readl(&clkrst->crc_rst_dev_l);
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reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_l);
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/* Assert Reset to SDMMC3 */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */
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writel(reg, &clkrst->crc_rst_dev_u);
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/* Enable clk to SDMMC3 */
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reg = readl(&clkrst->crc_clk_out_enb_u);
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reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */
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writel(reg, &clkrst->crc_clk_out_enb_u);
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/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
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reg = readl(&clkrst->crc_clk_src_sdmmc3);
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reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
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reg |= (10 << 1); /* n-1, 11-1 shl 1 */
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writel(reg, &clkrst->crc_clk_src_sdmmc3);
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/* wait for 2us */
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udelay(2);
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/* De-assert reset to SDMMC3 */
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reg = readl(&clkrst->crc_rst_dev_u);
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reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */
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writel(reg, &clkrst->crc_rst_dev_u);
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}
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 reg;
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/* SDMMC4 */
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/* config 2, x8 on 2nd set of pins */
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reg = readl(&pmt->pmt_ctl_a);
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reg |= (3 << 16); /* ATB_SEL [17:16] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_a);
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reg = readl(&pmt->pmt_ctl_b);
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reg |= (3 << 0); /* GMA_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_b);
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reg = readl(&pmt->pmt_ctl_d);
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reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_a);
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reg &= ~Z_ATB; /* Z_ATB = normal (0) */
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reg &= ~Z_GMA; /* Z_GMA = normal (0) */
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writel(reg, &pmt->pmt_tri_a);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_GME; /* Z_GME = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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/* SDMMC3 */
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/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
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reg = readl(&pmt->pmt_ctl_d);
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reg &= 0xFFFF03FF;
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reg |= (2 << 10); /* SDB_SEL [11:10] = 01 SDIO3 */
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reg |= (2 << 12); /* SDC_SEL [13:12] = 01 SDIO3 */
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reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
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writel(reg, &pmt->pmt_ctl_d);
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reg = readl(&pmt->pmt_tri_b);
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reg &= ~Z_SDC; /* Z_SDC = normal (0) */
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reg &= ~Z_SDD; /* Z_SDD = normal (0) */
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writel(reg, &pmt->pmt_tri_b);
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reg = readl(&pmt->pmt_tri_d);
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reg &= ~Z_SDB; /* Z_SDB = normal (0) */
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writel(reg, &pmt->pmt_tri_d);
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}
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/*
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* Routine: clock_init
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* Description: Do individual peripheral clock reset/enables
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*/
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void clock_init(void)
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{
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clock_init_uart();
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}
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pin_mux_uart();
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}
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/*
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* Routine: gpio_init
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* Description: Do individual peripheral GPIO configs
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*/
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void gpio_init(void)
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{
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gpio_config_uart();
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}
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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/* board id for Linux */
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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return 0;
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}
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#ifdef CONFIG_TEGRA2_MMC
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Enable clocks, muxes, etc. for SDMMC controllers */
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clock_init_mmc();
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pin_mux_mmc();
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debug("board_mmc_init: init eMMC\n");
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/* init dev 0, eMMC chip, with 4-bit bus */
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tegra2_mmc_init(0, 4);
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debug("board_mmc_init: init SD slot\n");
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/* init dev 1, SD slot, with 4-bit bus */
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tegra2_mmc_init(1, 4);
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return 0;
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}
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/* this is a weak define that we are overriding */
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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debug("board_mmc_getcd called\n");
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/*
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* Hard-code CD presence for now. Need to add GPIO inputs
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* for Seaboard & Harmony (& Kaen/Aebl/Wario?)
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*/
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*cd = 1;
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return 0;
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}
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#endif
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