upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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241 lines
7.6 KiB
241 lines
7.6 KiB
/*
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*
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* Functions for omap5 based boards.
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*
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* (C) Copyright 2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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* Sricharan <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/sizes.h>
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#include <asm/utils.h>
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#include <asm/arch/gpio.h>
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#include <asm/emif.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
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static struct gpio_bank gpio_bank_54xx[6] = {
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{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
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#ifdef CONFIG_SPL_BUILD
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/* LPDDR2 specific IO settings */
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static void io_settings_lpddr2(void)
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{
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const struct ctrl_ioregs *ioregs;
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get_ioregs(&ioregs);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
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writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
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writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
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writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
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}
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/* DDR3 specific IO settings */
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static void io_settings_ddr3(void)
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{
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u32 io_settings = 0;
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const struct ctrl_ioregs *ioregs;
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get_ioregs(&ioregs);
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writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
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writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
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writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
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writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
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writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
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writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
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/* omap5432 does not use lpddr2 */
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
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writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
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writel(ioregs->ctrl_emif_sdram_config_ext,
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(*ctrl)->control_emif1_sdram_config_ext);
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writel(ioregs->ctrl_emif_sdram_config_ext,
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(*ctrl)->control_emif2_sdram_config_ext);
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/* Disable DLL select */
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io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
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& 0xFFEFFFFF);
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writel(io_settings,
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(*ctrl)->control_port_emif1_sdram_config);
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io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
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& 0xFFEFFFFF);
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writel(io_settings,
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(*ctrl)->control_port_emif2_sdram_config);
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}
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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void do_io_settings(void)
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{
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u32 io_settings = 0, mask = 0;
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/* Impedance settings EMMC, C2C 1,2, hsi2 */
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mask = (ds_mask << 2) | (ds_mask << 8) |
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(ds_mask << 16) | (ds_mask << 18);
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io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
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(~mask);
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io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
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(ds_45_ohm << 18) | (ds_60_ohm << 2);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
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/* Impedance settings Mcspi2 */
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mask = (ds_mask << 30);
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io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
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(~mask);
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io_settings |= (ds_60_ohm << 30);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
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/* Impedance settings C2C 3,4 */
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mask = (ds_mask << 14) | (ds_mask << 16);
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io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
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(~mask);
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io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
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writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
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/* Slew rate settings EMMC, C2C 1,2 */
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mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
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io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
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(~mask);
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io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
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/* Slew rate settings hsi2, Mcspi2 */
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mask = (sc_mask << 24) | (sc_mask << 28);
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io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
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(~mask);
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io_settings |= (sc_fast << 28) | (sc_fast << 24);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
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/* Slew rate settings C2C 3,4 */
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mask = (sc_mask << 16) | (sc_mask << 18);
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io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
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(~mask);
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io_settings |= (sc_na << 16) | (sc_na << 18);
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writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
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/* impedance and slew rate settings for usb */
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mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
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(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
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io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
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(~mask);
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io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
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(ds_60_ohm << 23) | (sc_fast << 20) |
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(sc_fast << 17) | (sc_fast << 14);
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writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
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io_settings_lpddr2();
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else
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io_settings_ddr3();
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/* Efuse settings */
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writel(EFUSE_1, (*ctrl)->control_efuse_1);
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writel(EFUSE_2, (*ctrl)->control_efuse_2);
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writel(EFUSE_3, (*ctrl)->control_efuse_3);
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writel(EFUSE_4, (*ctrl)->control_efuse_4);
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}
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#endif
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void config_data_eye_leveling_samples(u32 emif_base)
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{
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/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
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if (emif_base == EMIF1_BASE)
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writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
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(*ctrl)->control_emif1_sdram_config_ext);
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else if (emif_base == EMIF2_BASE)
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writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
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(*ctrl)->control_emif2_sdram_config_ext);
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}
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void init_omap_revision(void)
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{
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/*
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* For some of the ES2/ES1 boards ID_CODE is not reliable:
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* Also, ES1 and ES2 have different ARM revisions
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* So use ARM revision for identification
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*/
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unsigned int rev = cortex_rev();
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP5430_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5430_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP5432_ES1_0;
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if (rev == MIDR_CORTEX_A15_R2P2)
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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case OMAP5430_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5430_ES2_0;
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break;
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case OMAP5432_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP5432_ES2_0;
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break;
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default:
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*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
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}
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}
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void reset_cpu(ulong ignored)
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{
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u32 omap_rev = omap_revision();
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/*
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* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
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* So use cold reset in case instead.
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*/
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if (omap_rev == OMAP5430_ES1_0)
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writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
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else
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writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
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}
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