upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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418 lines
10 KiB
418 lines
10 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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static void read_hw_vers (void);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/* single read (offset 0x00 in upm ram) */
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0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
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0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
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/* burst read (offset 0x08 in upm ram) */
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0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
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0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
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0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* single write (offset 0x18 in upm ram) */
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0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
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0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
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/* burst write (offset 0x20 in upm ram) */
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0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
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0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
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/* init part1 (offset 0x28 in upm ram) */
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0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
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0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* refresh (offset 0x30 in upm ram) */
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0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
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/* init part2 (offset 0x34 in upm ram) */
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0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
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0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
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/* exception (offset 0x3C in upm ram) */
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0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test ETX ID string (ETX_xxx...)
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*
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* Return 1 always.
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*/
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned char *s = getenv ("serial#");
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unsigned char *e;
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puts ("Board: ");
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#ifdef SB_ETX094
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gd->board_type = 0; /* 0 = 2SDRAM-Device */
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#else
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gd->board_type = 1; /* 1 = 1SDRAM-Device */
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#endif
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if (!s || strncmp (s, "ETX_", 4)) {
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puts ("### No HW ID - assuming ETX_094\n");
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read_hw_vers ();
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return (0);
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}
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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putc ('\n');
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read_hw_vers ();
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size_b0, size_b1, size8, size9;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */
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/* A3(SDRAM)=0 => Bursttype = Sequential
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* A2-A0(SDRAM)=010 => Burst length = 4
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* A4-A6(SDRAM)=010 => CasLat=2
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*/
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CFG_OR2_PRELIM;
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memctl->memc_br2 = CFG_BR2_PRELIM;
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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}
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */
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memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */
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udelay (1);
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */
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memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */
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udelay (1);
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}
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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if (board_type == 0) { /* "L" type boards have only one bank SDRAM */
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/*
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* Check Bank 1 Memory Size
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* use current column settings
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* [9 column SDRAM may also be used in 8 column mode,
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* but then only half the real size will be used.]
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*/
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size_b1 =
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dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
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SDRAM_MAX_SIZE);
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/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
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} else {
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size_b1 = 0;
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /*DIV16 */
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udelay (1000);
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}
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/*
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* Final mapping: map bigger bank first
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*/
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if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
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memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b0 > 0) {
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/*
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* Position Bank 0 immediately above Bank 1
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*/
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memctl->memc_or2 =
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((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b1;
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} else {
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unsigned long reg;
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/*
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* No bank 0
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*
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* invalidate bank
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*/
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memctl->memc_br2 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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} else { /* SDRAM Bank 0 is bigger - map first */
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b1 > 0) {
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/*
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* Position Bank 1 immediately above Bank 0
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*/
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memctl->memc_or3 =
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((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b0;
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} else {
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unsigned long reg;
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br3 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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}
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udelay (10000);
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return (size_b0 + size_b1);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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/* ------------------------------------------------------------------------- */
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/* HW-ID Table (Bits: 2^9;2^7;2^5) */
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#define HW_ID_0 0x0000
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#define HW_ID_1 0x0020
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#define HW_ID_2 0x0080
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#define HW_ID_3 0x00a0
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#define HW_ID_4 0x0200
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#define HW_ID_5 0x0220
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#define HW_ID_6 0x0280
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#define HW_ID_7 0x02a0
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void read_hw_vers ()
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{
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unsigned short rd_msk = 0x02A0;
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/* HW-ID pin-definition */
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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immr->im_ioport.iop_pddir &= ~(rd_msk);
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immr->im_ioport.iop_pdpar &= ~(rd_msk);
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/* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
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/* Check the HW-ID */
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printf ("HW-Version: ");
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switch (immr->im_ioport.iop_pddat & rd_msk) {
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case HW_ID_0:
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printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
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break;
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case HW_ID_1:
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printf ("V0.9 / W50037-Q1-D6-1\n");
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break;
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case HW_ID_2:
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printf ("NOT USED - assuming ID#2\n");
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break;
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case HW_ID_3:
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printf ("NOT USED - assuming ID#3\n");
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break;
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case HW_ID_4:
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printf ("NOT USED - assuming ID#4\n");
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break;
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case HW_ID_5:
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printf ("NOT USED - assuming ID#5\n");
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break;
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case HW_ID_6:
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printf ("NOT USED - assuming ID#6\n");
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break;
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case HW_ID_7:
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printf ("NOT USED - assuming ID#7\n");
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break;
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default:
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printf ("###Error###\n");
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break;
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}
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}
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/* ------------------------------------------------------------------------- */
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