upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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166 lines
3.7 KiB
166 lines
3.7 KiB
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __GDSYS_FPGA_H
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#define __GDSYS_FPGA_H
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int init_func_fpga(void);
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enum {
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FPGA_STATE_DONE_FAILED = 1 << 0,
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FPGA_STATE_REFLECTION_FAILED = 1 << 1,
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FPGA_STATE_PLATFORM = 1 << 2,
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};
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int get_fpga_state(unsigned dev);
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void print_fpga_state(unsigned dev);
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int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
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int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
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extern struct ihs_fpga *fpga_ptr[];
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#define FPGA_SET_REG(ix, fld, val) \
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fpga_set_reg((ix), \
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&fpga_ptr[ix]->fld, \
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offsetof(struct ihs_fpga, fld), \
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val)
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#define FPGA_GET_REG(ix, fld, val) \
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fpga_get_reg((ix), \
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&fpga_ptr[ix]->fld, \
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offsetof(struct ihs_fpga, fld), \
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val)
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struct ihs_gpio {
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u16 read;
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u16 clear;
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u16 set;
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};
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struct ihs_i2c {
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u16 write_mailbox;
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u16 write_mailbox_ext;
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u16 read_mailbox;
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u16 read_mailbox_ext;
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};
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struct ihs_osd {
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u16 version;
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u16 features;
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u16 control;
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u16 xy_size;
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u16 xy_scale;
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u16 x_pos;
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u16 y_pos;
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};
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#ifdef CONFIG_NEO
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[8187]; /* 0x0008 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IO
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[5]; /* 0x0008 */
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u16 quad_serdes_reset; /* 0x0012 */
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u16 reserved_1[8181]; /* 0x0014 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IO64
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struct ihs_fpga_channel {
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u16 status_int;
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u16 config_int;
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u16 switch_connect_config;
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u16 tx_destination;
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};
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struct ihs_fpga_hicb {
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u16 status_int;
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u16 config_int;
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};
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_features; /* 0x0004 */
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u16 fpga_version; /* 0x0006 */
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u16 reserved_0[5]; /* 0x0008 */
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u16 quad_serdes_reset; /* 0x0012 */
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u16 reserved_1[502]; /* 0x0014 */
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struct ihs_fpga_channel ch[32]; /* 0x0400 */
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struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
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u16 reserved_2[7487]; /* 0x0580 */
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u16 reflection_high; /* 0x3ffe */
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};
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#endif
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#ifdef CONFIG_IOCON
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[6]; /* 0x0008 */
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struct ihs_gpio gpio; /* 0x0014 */
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u16 mpc3w_control; /* 0x001a */
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u16 reserved_1[19]; /* 0x001c */
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u16 videocontrol; /* 0x0042 */
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u16 reserved_2[14]; /* 0x0044 */
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u16 mc_int; /* 0x0060 */
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u16 mc_int_en; /* 0x0062 */
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u16 mc_status; /* 0x0064 */
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u16 mc_control; /* 0x0066 */
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u16 mc_tx_data; /* 0x0068 */
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u16 mc_tx_address; /* 0x006a */
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u16 mc_tx_cmd; /* 0x006c */
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u16 mc_res; /* 0x006e */
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u16 mc_rx_cmd_status; /* 0x0070 */
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u16 mc_rx_data; /* 0x0072 */
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u16 reserved_3[69]; /* 0x0074 */
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u16 reflection_high; /* 0x00fe */
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struct ihs_osd osd; /* 0x0100 */
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u16 reserved_4[889]; /* 0x010e */
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u16 videomem[31736]; /* 0x0800 */
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};
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#endif
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#ifdef CONFIG_DLVISION_10G
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struct ihs_fpga {
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u16 reflection_low; /* 0x0000 */
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u16 versions; /* 0x0002 */
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u16 fpga_version; /* 0x0004 */
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u16 fpga_features; /* 0x0006 */
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u16 reserved_0[10]; /* 0x0008 */
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u16 extended_interrupt; /* 0x001c */
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u16 reserved_1[9]; /* 0x001e */
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struct ihs_i2c i2c; /* 0x0030 */
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u16 reserved_2[16]; /* 0x0038 */
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u16 mpc3w_control; /* 0x0058 */
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u16 reserved_3[34]; /* 0x005a */
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u16 videocontrol; /* 0x009e */
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u16 reserved_4[176]; /* 0x00a0 */
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struct ihs_osd osd; /* 0x0200 */
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u16 reserved_5[761]; /* 0x020e */
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u16 videomem[31736]; /* 0x0800 */
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};
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#endif
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#endif
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