upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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558 lines
15 KiB
558 lines
15 KiB
/*
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* Machine Specific Values for ORIGEN board based on S5PV310
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*
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* Copyright (C) 2011 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ORIGEN_SETUP_H
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#define _ORIGEN_SETUP_H
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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/* Offsets of clock registers (sources and dividers) */
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#define CLK_SRC_CPU_OFFSET 0x14200
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#define CLK_DIV_CPU0_OFFSET 0x14500
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#define CLK_DIV_CPU1_OFFSET 0x14504
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#define CLK_SRC_DMC_OFFSET 0x10200
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#define CLK_DIV_DMC0_OFFSET 0x10500
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#define CLK_DIV_DMC1_OFFSET 0x10504
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#define CLK_SRC_TOP0_OFFSET 0xC210
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#define CLK_SRC_TOP1_OFFSET 0xC214
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#define CLK_DIV_TOP_OFFSET 0xC510
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#define CLK_SRC_LEFTBUS_OFFSET 0x4200
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#define CLK_DIV_LEFTBUS_OFFSET 0x4500
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#define CLK_SRC_RIGHTBUS_OFFSET 0x8200
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#define CLK_DIV_RIGHTBUS_OFFSET 0x8500
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#define CLK_SRC_FSYS_OFFSET 0xC240
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#define CLK_DIV_FSYS1_OFFSET 0xC544
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#define CLK_DIV_FSYS2_OFFSET 0xC548
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#define CLK_DIV_FSYS3_OFFSET 0xC54C
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#define CLK_SRC_PERIL0_OFFSET 0xC250
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#define CLK_DIV_PERIL0_OFFSET 0xC550
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#define CLK_SRC_LCD0_OFFSET 0xC234
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#define APLL_LOCK_OFFSET 0x14000
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#define MPLL_LOCK_OFFSET 0x14008
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#define APLL_CON0_OFFSET 0x14100
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#define APLL_CON1_OFFSET 0x14104
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#define MPLL_CON0_OFFSET 0x14108
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#define MPLL_CON1_OFFSET 0x1410C
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#define EPLL_LOCK_OFFSET 0xC010
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#define VPLL_LOCK_OFFSET 0xC020
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#define EPLL_CON0_OFFSET 0xC110
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#define EPLL_CON1_OFFSET 0xC114
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#define VPLL_CON0_OFFSET 0xC120
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#define VPLL_CON1_OFFSET 0xC124
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/* DMC: DRAM Controllor Register offsets */
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#define DMC_CONCONTROL 0x00
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#define DMC_MEMCONTROL 0x04
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#define DMC_MEMCONFIG0 0x08
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#define DMC_MEMCONFIG1 0x0C
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#define DMC_DIRECTCMD 0x10
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#define DMC_PRECHCONFIG 0x14
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#define DMC_PHYCONTROL0 0x18
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#define DMC_PHYCONTROL1 0x1C
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#define DMC_PHYCONTROL2 0x20
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#define DMC_TIMINGAREF 0x30
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#define DMC_TIMINGROW 0x34
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#define DMC_TIMINGDATA 0x38
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#define DMC_TIMINGPOWER 0x3C
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#define DMC_PHYZQCONTROL 0x44
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/* Bus Configuration Register Address */
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#define ASYNC_CONFIG 0x10010350
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/* MIU Config Register Offsets*/
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#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
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#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
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/* Offset for inform registers */
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#define INFORM0_OFFSET 0x800
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#define INFORM1_OFFSET 0x804
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/* GPIO Offsets for UART: GPIO Contol Register */
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#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
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#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
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/* UART Register offsets */
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#define ULCON_OFFSET 0x00
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#define UCON_OFFSET 0x04
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#define UFCON_OFFSET 0x08
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#define UBRDIV_OFFSET 0x28
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#define UFRACVAL_OFFSET 0x2C
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/* TZPC : Register Offsets */
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#define TZPC0_BASE 0x10110000
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#define TZPC1_BASE 0x10120000
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#define TZPC2_BASE 0x10130000
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#define TZPC3_BASE 0x10140000
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#define TZPC4_BASE 0x10150000
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#define TZPC5_BASE 0x10160000
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#define TZPC_DECPROT0SET_OFFSET 0x804
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#define TZPC_DECPROT1SET_OFFSET 0x810
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#define TZPC_DECPROT2SET_OFFSET 0x81C
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#define TZPC_DECPROT3SET_OFFSET 0x828
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/* CLK_SRC_CPU */
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#define MUX_HPM_SEL_MOUTAPLL 0x0
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#define MUX_HPM_SEL_SCLKMPLL 0x1
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#define MUX_CORE_SEL_MOUTAPLL 0x0
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#define MUX_CORE_SEL_SCLKMPLL 0x1
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#define MUX_MPLL_SEL_FILPLL 0x0
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#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
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#define MUX_APLL_SEL_FILPLL 0x0
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#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
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#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
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| (MUX_CORE_SEL_MOUTAPLL << 16) \
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| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
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| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
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/* CLK_DIV_CPU0 */
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#define APLL_RATIO 0x0
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#define PCLK_DBG_RATIO 0x1
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#define ATB_RATIO 0x3
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#define PERIPH_RATIO 0x3
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#define COREM1_RATIO 0x7
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#define COREM0_RATIO 0x3
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#define CORE_RATIO 0x0
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#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
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| (PCLK_DBG_RATIO << 20) \
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| (ATB_RATIO << 16) \
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| (PERIPH_RATIO << 12) \
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| (COREM1_RATIO << 8) \
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| (COREM0_RATIO << 4) \
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| (CORE_RATIO << 0))
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/* CLK_DIV_CPU1 */
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#define HPM_RATIO 0x0
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#define COPY_RATIO 0x3
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#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
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/* CLK_SRC_DMC */
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#define MUX_PWI_SEL_XXTI 0x0
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#define MUX_PWI_SEL_XUSBXTI 0x1
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#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
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#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
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#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
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#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
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#define MUX_PWI_SEL_SCLKMPLL 0x6
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#define MUX_PWI_SEL_SCLKEPLL 0x7
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#define MUX_PWI_SEL_SCLKVPLL 0x8
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#define MUX_DPHY_SEL_SCLKMPLL 0x0
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#define MUX_DPHY_SEL_SCLKAPLL 0x1
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#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
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#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
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#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
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| (MUX_DPHY_SEL_SCLKMPLL << 8) \
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| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
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/* CLK_DIV_DMC0 */
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#define CORE_TIMERS_RATIO 0x1
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#define COPY2_RATIO 0x3
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#define DMCP_RATIO 0x1
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#define DMCD_RATIO 0x1
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#define DMC_RATIO 0x1
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#define DPHY_RATIO 0x1
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#define ACP_PCLK_RATIO 0x1
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#define ACP_RATIO 0x3
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#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
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| (COPY2_RATIO << 24) \
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| (DMCP_RATIO << 20) \
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| (DMCD_RATIO << 16) \
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| (DMC_RATIO << 12) \
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| (DPHY_RATIO << 8) \
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| (ACP_PCLK_RATIO << 4) \
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| (ACP_RATIO << 0))
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/* CLK_DIV_DMC1 */
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#define DPM_RATIO 0x1
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#define DVSEM_RATIO 0x1
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#define PWI_RATIO 0x1
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#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
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| (DVSEM_RATIO << 16) \
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| (PWI_RATIO << 8))
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/* CLK_SRC_TOP0 */
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#define MUX_ONENAND_SEL_ACLK_133 0x0
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#define MUX_ONENAND_SEL_ACLK_160 0x1
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#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
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#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
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#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
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#define MUX_VPLL_SEL_FINPLL 0x0
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#define MUX_VPLL_SEL_FOUTVPLL 0x1
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#define MUX_EPLL_SEL_FINPLL 0x0
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#define MUX_EPLL_SEL_FOUTEPLL 0x1
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#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
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#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
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#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
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| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
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| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
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| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
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| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
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| (MUX_VPLL_SEL_FINPLL << 8) \
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| (MUX_EPLL_SEL_FINPLL << 4)\
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| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
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/* CLK_SRC_TOP1 */
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#define VPLLSRC_SEL_FINPLL 0x0
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#define VPLLSRC_SEL_SCLKHDMI24M 0x1
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#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
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/* CLK_DIV_TOP */
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#define ONENAND_RATIO 0x0
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#define ACLK_133_RATIO 0x5
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#define ACLK_160_RATIO 0x4
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#define ACLK_100_RATIO 0x7
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#define ACLK_200_RATIO 0x3
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#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
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| (ACLK_133_RATIO << 12)\
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| (ACLK_160_RATIO << 8) \
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| (ACLK_100_RATIO << 4) \
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| (ACLK_200_RATIO << 0))
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/* CLK_SRC_LEFTBUS */
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#define MUX_GDL_SEL_SCLKMPLL 0x0
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#define MUX_GDL_SEL_SCLKAPLL 0x1
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#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
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/* CLK_DIV_LEFTBUS */
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#define GPL_RATIO 0x1
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#define GDL_RATIO 0x3
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#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
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/* CLK_SRC_RIGHTBUS */
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#define MUX_GDR_SEL_SCLKMPLL 0x0
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#define MUX_GDR_SEL_SCLKAPLL 0x1
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#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
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/* CLK_DIV_RIGHTBUS */
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#define GPR_RATIO 0x1
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#define GDR_RATIO 0x3
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#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
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/* CLK_SRS_FSYS: 6 = SCLKMPLL */
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#define SATA_SEL_SCLKMPLL 0
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#define SATA_SEL_SCLKAPLL 1
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#define MMC_SEL_XXTI 0
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#define MMC_SEL_XUSBXTI 1
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#define MMC_SEL_SCLK_HDMI24M 2
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#define MMC_SEL_SCLK_USBPHY0 3
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#define MMC_SEL_SCLK_USBPHY1 4
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#define MMC_SEL_SCLK_HDMIPHY 5
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#define MMC_SEL_SCLKMPLL 6
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#define MMC_SEL_SCLKEPLL 7
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#define MMC_SEL_SCLKVPLL 8
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#define MMCC0_SEL MMC_SEL_SCLKMPLL
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#define MMCC1_SEL MMC_SEL_SCLKMPLL
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#define MMCC2_SEL MMC_SEL_SCLKMPLL
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#define MMCC3_SEL MMC_SEL_SCLKMPLL
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#define MMCC4_SEL MMC_SEL_SCLKMPLL
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#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
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| (MMCC4_SEL << 16) \
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| (MMCC3_SEL << 12) \
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| (MMCC2_SEL << 8) \
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| (MMCC1_SEL << 4) \
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| (MMCC0_SEL << 0))
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/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
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/* CLK_DIV_FSYS1 */
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#define MMC0_RATIO 0xF
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#define MMC0_PRE_RATIO 0x0
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#define MMC1_RATIO 0xF
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#define MMC1_PRE_RATIO 0x0
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#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
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| (MMC1_RATIO << 16) \
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| (MMC0_PRE_RATIO << 8) \
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| (MMC0_RATIO << 0))
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/* CLK_DIV_FSYS2 */
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#define MMC2_RATIO 0xF
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#define MMC2_PRE_RATIO 0x0
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#define MMC3_RATIO 0xF
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#define MMC3_PRE_RATIO 0x0
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#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
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| (MMC3_RATIO << 16) \
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| (MMC2_PRE_RATIO << 8) \
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| (MMC2_RATIO << 0))
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/* CLK_DIV_FSYS3 */
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#define MMC4_RATIO 0xF
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#define MMC4_PRE_RATIO 0x0
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#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
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| (MMC4_RATIO << 0))
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/* CLK_SRC_PERIL0 */
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#define UART_SEL_XXTI 0
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#define UART_SEL_XUSBXTI 1
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#define UART_SEL_SCLK_HDMI24M 2
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#define UART_SEL_SCLK_USBPHY0 3
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#define UART_SEL_SCLK_USBPHY1 4
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#define UART_SEL_SCLK_HDMIPHY 5
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#define UART_SEL_SCLKMPLL 6
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#define UART_SEL_SCLKEPLL 7
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#define UART_SEL_SCLKVPLL 8
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#define UART0_SEL UART_SEL_SCLKMPLL
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#define UART1_SEL UART_SEL_SCLKMPLL
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#define UART2_SEL UART_SEL_SCLKMPLL
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#define UART3_SEL UART_SEL_SCLKMPLL
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#define UART4_SEL UART_SEL_SCLKMPLL
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#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
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| (UART3_SEL << 12) \
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| (UART2_SEL << 8) \
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| (UART1_SEL << 4) \
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| (UART0_SEL << 0))
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/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
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/* CLK_DIV_PERIL0 */
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#define UART0_RATIO 7
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#define UART1_RATIO 7
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#define UART2_RATIO 7
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#define UART3_RATIO 7
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#define UART4_RATIO 7
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#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
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| (UART3_RATIO << 12) \
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| (UART2_RATIO << 8) \
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| (UART1_RATIO << 4) \
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| (UART0_RATIO << 0))
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/* CLK_SRC_LCD0 */
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#define FIMD_SEL_SCLKMPLL 6
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#define MDNIE0_SEL_XUSBXTI 1
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#define MDNIE_PWM0_SEL_XUSBXTI 1
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#define MIPI0_SEL_XUSBXTI 1
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#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
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| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
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| (MDNIE0_SEL_XUSBXTI << 4) \
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| (FIMD_SEL_SCLKMPLL << 0))
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/* Required period to generate a stable clock output */
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/* PLL_LOCK_TIME */
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#define PLL_LOCKTIME 0x1C20
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/* PLL Values */
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#define DISABLE 0
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#define ENABLE 1
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#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
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| (mdiv << 16) \
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| (pdiv << 8) \
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| (sdiv << 0))
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/* APLL_CON0 */
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#define APLL_MDIV 0xFA
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#define APLL_PDIV 0x6
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#define APLL_SDIV 0x1
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#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
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/* APLL_CON1 */
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#define APLL_AFC_ENB 0x1
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#define APLL_AFC 0xC
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#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
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/* MPLL_CON0 */
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#define MPLL_MDIV 0xC8
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#define MPLL_PDIV 0x6
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#define MPLL_SDIV 0x1
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#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
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/* MPLL_CON1 */
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#define MPLL_AFC_ENB 0x0
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#define MPLL_AFC 0x1C
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#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
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/* EPLL_CON0 */
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#define EPLL_MDIV 0x30
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#define EPLL_PDIV 0x3
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#define EPLL_SDIV 0x2
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#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
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/* EPLL_CON1 */
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#define EPLL_K 0x0
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#define EPLL_CON1_VAL (EPLL_K >> 0)
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/* VPLL_CON0 */
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#define VPLL_MDIV 0x35
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#define VPLL_PDIV 0x3
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#define VPLL_SDIV 0x2
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#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
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|
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/* VPLL_CON1 */
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#define VPLL_SSCG_EN DISABLE
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#define VPLL_SEL_PF_DN_SPREAD 0x0
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#define VPLL_MRR 0x11
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#define VPLL_MFR 0x0
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#define VPLL_K 0x400
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#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
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| (VPLL_SEL_PF_DN_SPREAD << 29) \
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| (VPLL_MRR << 24) \
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| (VPLL_MFR << 16) \
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| (VPLL_K << 0))
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/*
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* UART GPIO_A0/GPIO_A1 Control Register Value
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* 0x2: UART Function
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*/
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#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
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#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
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|
|
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/* ULCON: UART Line Control Value 8N1 */
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#define WORD_LEN_5_BIT 0x00
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#define WORD_LEN_6_BIT 0x01
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#define WORD_LEN_7_BIT 0x02
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#define WORD_LEN_8_BIT 0x03
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|
|
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#define STOP_BIT_1 0x00
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#define STOP_BIT_2 0x01
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|
|
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#define NO_PARITY 0x00
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#define ODD_PARITY 0x4
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#define EVEN_PARITY 0x5
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#define FORCED_PARITY_CHECK_AS_1 0x6
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#define FORCED_PARITY_CHECK_AS_0 0x7
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|
|
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#define INFRAMODE_NORMAL 0x00
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#define INFRAMODE_INFRARED 0x01
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|
|
|
#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \
|
|
| (NO_PARITY << 3) \
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| (STOP_BIT_1 << 2) \
|
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| (WORD_LEN_8_BIT << 0))
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|
|
|
/*
|
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* UCON: UART Control Value
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* Tx_interrupt Type: Level
|
|
* Rx_interrupt Type: Level
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|
* Rx Timeout Enabled: Yes
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|
* Rx-Error Atatus_Int Enable: Yes
|
|
* Loop_Back: No
|
|
* Break Signal: No
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* Transmit mode : Interrupt request/polling
|
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* Receive mode : Interrupt request/polling
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*/
|
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#define TX_PULSE_INTERRUPT 0
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|
#define TX_LEVEL_INTERRUPT 1
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#define RX_PULSE_INTERRUPT 0
|
|
#define RX_LEVEL_INTERRUPT 1
|
|
|
|
#define RX_TIME_OUT ENABLE
|
|
#define RX_ERROR_STATE_INT_ENB ENABLE
|
|
#define LOOP_BACK DISABLE
|
|
#define BREAK_SIGNAL DISABLE
|
|
|
|
#define TX_MODE_DISABLED 0X00
|
|
#define TX_MODE_IRQ_OR_POLL 0X01
|
|
#define TX_MODE_DMA 0X02
|
|
|
|
#define RX_MODE_DISABLED 0X00
|
|
#define RX_MODE_IRQ_OR_POLL 0X01
|
|
#define RX_MODE_DMA 0X02
|
|
|
|
#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \
|
|
| (RX_LEVEL_INTERRUPT << 8) \
|
|
| (RX_TIME_OUT << 7) \
|
|
| (RX_ERROR_STATE_INT_ENB << 6) \
|
|
| (LOOP_BACK << 5) \
|
|
| (BREAK_SIGNAL << 4) \
|
|
| (TX_MODE_IRQ_OR_POLL << 2) \
|
|
| (RX_MODE_IRQ_OR_POLL << 0))
|
|
|
|
/*
|
|
* UFCON: UART FIFO Control Value
|
|
* Tx FIFO Trigger LEVEL: 2 Bytes (001)
|
|
* Rx FIFO Trigger LEVEL: 2 Bytes (001)
|
|
* Tx Fifo Reset: No
|
|
* Rx Fifo Reset: No
|
|
* FIFO Enable: Yes
|
|
*/
|
|
#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00
|
|
#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1
|
|
#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2
|
|
#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3
|
|
#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4
|
|
#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5
|
|
#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6
|
|
#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7
|
|
|
|
#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0
|
|
#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1
|
|
#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2
|
|
#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3
|
|
#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4
|
|
#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5
|
|
#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6
|
|
#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7
|
|
|
|
#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES
|
|
#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES
|
|
#define TX_FIFO_RESET DISABLE
|
|
#define RX_FIFO_RESET DISABLE
|
|
#define FIFO_ENABLE ENABLE
|
|
#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \
|
|
| (RX_FIFO_TRIGGER_LEVEL << 4) \
|
|
| (TX_FIFO_RESET << 2) \
|
|
| (RX_FIFO_RESET << 1) \
|
|
| (FIFO_ENABLE << 0))
|
|
/*
|
|
* Baud Rate Division Value
|
|
* 115200 BAUD:
|
|
* UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
|
|
* UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
|
|
*/
|
|
#define UBRDIV_VAL 0x35
|
|
|
|
/*
|
|
* Fractional Part of Baud Rate Divisor:
|
|
* 115200 BAUD:
|
|
* UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
|
|
* UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
|
|
*/
|
|
#define UFRACVAL_VAL 0x4
|
|
|
|
/*
|
|
* TZPC Register Value :
|
|
* R0SIZE: 0x0 : Size of secured ram
|
|
*/
|
|
#define R0SIZE 0x0
|
|
|
|
/*
|
|
* TZPC Decode Protection Register Value :
|
|
* DECPROTXSET: 0xFF : Set Decode region to non-secure
|
|
*/
|
|
#define DECPROTXSET 0xFF
|
|
#endif
|
|
|