upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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147 lines
5.4 KiB
147 lines
5.4 KiB
/*
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* Freescale i.MX28 RTC Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __MX28_REGS_RTC_H__
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#define __MX28_REGS_RTC_H__
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#include <asm/arch/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mx28_rtc_regs {
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mx28_reg_32(hw_rtc_ctrl)
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mx28_reg_32(hw_rtc_stat)
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mx28_reg_32(hw_rtc_milliseconds)
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mx28_reg_32(hw_rtc_seconds)
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mx28_reg_32(hw_rtc_rtc_alarm)
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mx28_reg_32(hw_rtc_watchdog)
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mx28_reg_32(hw_rtc_persistent0)
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mx28_reg_32(hw_rtc_persistent1)
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mx28_reg_32(hw_rtc_persistent2)
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mx28_reg_32(hw_rtc_persistent3)
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mx28_reg_32(hw_rtc_persistent4)
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mx28_reg_32(hw_rtc_persistent5)
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mx28_reg_32(hw_rtc_debug)
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mx28_reg_32(hw_rtc_version)
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};
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#endif
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#define RTC_CTRL_SFTRST (1 << 31)
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#define RTC_CTRL_CLKGATE (1 << 30)
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#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6)
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#define RTC_CTRL_FORCE_UPDATE (1 << 5)
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#define RTC_CTRL_WATCHDOGEN (1 << 4)
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#define RTC_CTRL_ONEMSEC_IRQ (1 << 3)
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#define RTC_CTRL_ALARM_IRQ (1 << 2)
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#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1)
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#define RTC_CTRL_ALARM_IRQ_EN (1 << 0)
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#define RTC_STAT_RTC_PRESENT (1 << 31)
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#define RTC_STAT_ALARM_PRESENT (1 << 30)
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#define RTC_STAT_WATCHDOG_PRESENT (1 << 29)
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#define RTC_STAT_XTAL32000_PRESENT (1 << 28)
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#define RTC_STAT_XTAL32768_PRESENT (1 << 27)
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#define RTC_STAT_STALE_REGS_MASK (0xff << 16)
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#define RTC_STAT_STALE_REGS_OFFSET 16
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#define RTC_STAT_NEW_REGS_MASK (0xff << 8)
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#define RTC_STAT_NEW_REGS_OFFSET 8
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#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff
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#define RTC_MILLISECONDS_COUNT_OFFSET 0
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#define RTC_SECONDS_COUNT_MASK 0xffffffff
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#define RTC_SECONDS_COUNT_OFFSET 0
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#define RTC_ALARM_VALUE_MASK 0xffffffff
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#define RTC_ALARM_VALUE_OFFSET 0
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#define RTC_WATCHDOG_COUNT_MASK 0xffffffff
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#define RTC_WATCHDOG_COUNT_OFFSET 0
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28)
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#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28)
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#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21)
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#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20)
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#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
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#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
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#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
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#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14)
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#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14
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#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14)
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#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14)
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#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14)
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#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
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#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8)
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#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8
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#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8)
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#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8)
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#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8)
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#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8)
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#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8)
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#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
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#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
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#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
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#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4)
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#define RTC_PERSISTENT0_LCK_SECS (1 << 3)
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#define RTC_PERSISTENT0_ALARM_EN (1 << 2)
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#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
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#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
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#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff
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#define RTC_PERSISTENT1_GENERAL_OFFSET 0
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#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080
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#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100
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#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200
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#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400
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#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800
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#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000
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#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff
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#define RTC_PERSISTENT2_GENERAL_OFFSET 0
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#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff
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#define RTC_PERSISTENT3_GENERAL_OFFSET 0
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#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff
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#define RTC_PERSISTENT4_GENERAL_OFFSET 0
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#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff
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#define RTC_PERSISTENT5_GENERAL_OFFSET 0
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#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1)
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#define RTC_DEBUG_WATCHDOG_RESET (1 << 0)
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#define RTC_VERSION_MAJOR_MASK (0xff << 24)
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#define RTC_VERSION_MAJOR_OFFSET 24
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#define RTC_VERSION_MINOR_MASK (0xff << 16)
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#define RTC_VERSION_MINOR_OFFSET 16
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#define RTC_VERSION_STEP_MASK 0xffff
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#define RTC_VERSION_STEP_OFFSET 0
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#endif /* __MX28_REGS_RTC_H__ */
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