upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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367 lines
16 KiB
367 lines
16 KiB
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*----------------------------------------------------------------------------+
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| FPGA registers and bit definitions
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+----------------------------------------------------------------------------*/
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/*
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* PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
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* TLB initialization makes it correspond to logical address 0x80001FF0.
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* => Done init_chip.s in bootlib
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*/
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#define FPGA_BASE_ADDR 0x80002000
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/*----------------------------------------------------------------------------+
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| Board Jumpers Setting Register
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| Board Settings provided by jumpers
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+----------------------------------------------------------------------------*/
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#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
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/* Boot from small flash */
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#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
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/* Operational Flash versus SRAM position in Memory Map */
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#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
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#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
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#define FPGA_SET_REG_SRAM_ABOVE 0x00
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/* Boot From NAND Flash */
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#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
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#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
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/* On Board PCI Arbiter Select */
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#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
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#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 1
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
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#define FPGA_SEL_1_REG_PHY_MASK 0xE0
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#define FPGA_SEL_1_REG_MII 0x80
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#define FPGA_SEL_1_REG_RMII 0x40
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#define FPGA_SEL_1_REG_SMII 0x20
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#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
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#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
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#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
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#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
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#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
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#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 2
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
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#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
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#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
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#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
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#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
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#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
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#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
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#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
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/* 1 = TC - output from 440EP */
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#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
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/* 1 = TC (output from 440EP) */
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#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
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#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
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#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
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/*----------------------------------------------------------------------------+
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| Functions Selection Register 3
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+----------------------------------------------------------------------------*/
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#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
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#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
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#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
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#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
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#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
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#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
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/*----------------------------------------------------------------------------+
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| Soft Reset Register
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+----------------------------------------------------------------------------*/
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#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
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#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
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#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
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#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
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#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
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/*----------------------------------------------------------------------------+
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| SDR Configuration registers
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+----------------------------------------------------------------------------*/
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#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
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#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
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#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
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#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
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#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
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#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
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#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
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#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
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/* Serial Device Enabled - Addr = 0xA8 */
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#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
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/* Serial Device Enabled - Addr = 0xA4 */
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#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
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/* Pin Straps Reg */
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#define SDR0_PSTRP0 0x0040
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#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
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#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
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/*----------------------------------------------------------------------------+
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| EBC Configuration Register - EBC0_CFG
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+----------------------------------------------------------------------------*/
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/* External Bus Three-State Control */
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#define EBC0_CFG_EBTC_DRIVEN 0x80000000
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/* Device-Paced Time-out Disable */
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#define EBC0_CFG_PTD_ENABLED 0x00000000
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/* Ready Timeout Count */
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#define EBC0_CFG_RTC_MASK 0x38000000
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#define EBC0_CFG_RTC_16PERCLK 0x00000000
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#define EBC0_CFG_RTC_32PERCLK 0x08000000
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#define EBC0_CFG_RTC_64PERCLK 0x10000000
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#define EBC0_CFG_RTC_128PERCLK 0x18000000
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#define EBC0_CFG_RTC_256PERCLK 0x20000000
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#define EBC0_CFG_RTC_512PERCLK 0x28000000
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#define EBC0_CFG_RTC_1024PERCLK 0x30000000
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#define EBC0_CFG_RTC_2048PERCLK 0x38000000
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/* External Master Priority Low */
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#define EBC0_CFG_EMPL_LOW 0x00000000
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#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
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#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
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#define EBC0_CFG_EMPL_HIGH 0x06000000
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/* External Master Priority High */
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#define EBC0_CFG_EMPH_LOW 0x00000000
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#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
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#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
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#define EBC0_CFG_EMPH_HIGH 0x01800000
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/* Chip Select Three-State Control */
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#define EBC0_CFG_CSTC_DRIVEN 0x00400000
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/* Burst Prefetch */
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#define EBC0_CFG_BPF_ONEDW 0x00000000
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#define EBC0_CFG_BPF_TWODW 0x00100000
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#define EBC0_CFG_BPF_FOURDW 0x00200000
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/* External Master Size */
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#define EBC0_CFG_EMS_8BIT 0x00000000
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/* Power Management Enable */
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#define EBC0_CFG_PME_DISABLED 0x00000000
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#define EBC0_CFG_PME_ENABLED 0x00020000
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/* Power Management Timer */
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#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
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/*----------------------------------------------------------------------------+
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| Peripheral Bank Configuration Register - EBC0_BnCR
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+----------------------------------------------------------------------------*/
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/* BAS - Base Address Select */
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#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
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/* BS - Bank Size */
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#define EBC0_BNCR_BS_MASK 0x000E0000
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#define EBC0_BNCR_BS_1MB 0x00000000
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#define EBC0_BNCR_BS_2MB 0x00020000
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#define EBC0_BNCR_BS_4MB 0x00040000
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#define EBC0_BNCR_BS_8MB 0x00060000
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#define EBC0_BNCR_BS_16MB 0x00080000
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#define EBC0_BNCR_BS_32MB 0x000A0000
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#define EBC0_BNCR_BS_64MB 0x000C0000
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#define EBC0_BNCR_BS_128MB 0x000E0000
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/* BU - Bank Usage */
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#define EBC0_BNCR_BU_MASK 0x00018000
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#define EBC0_BNCR_BU_RO 0x00008000
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#define EBC0_BNCR_BU_WO 0x00010000
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#define EBC0_BNCR_BU_RW 0x00018000
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/* BW - Bus Width */
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#define EBC0_BNCR_BW_MASK 0x00006000
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#define EBC0_BNCR_BW_8BIT 0x00000000
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#define EBC0_BNCR_BW_16BIT 0x00002000
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#define EBC0_BNCR_BW_32BIT 0x00004000
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/*----------------------------------------------------------------------------+
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| Peripheral Bank Access Parameters - EBC0_BnAP
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+----------------------------------------------------------------------------*/
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/* Burst Mode Enable */
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#define EBC0_BNAP_BME_ENABLED 0x80000000
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#define EBC0_BNAP_BME_DISABLED 0x00000000
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/* Transfert Wait */
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#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
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/* Chip Select On Timing */
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#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
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/* Output Enable On Timing */
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#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
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/* Write Back Enable On Timing */
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#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
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/* Write Back Enable Off Timing */
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#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
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/* Transfert Hold */
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#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
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/* PerReady Enable */
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#define EBC0_BNAP_RE_ENABLED 0x00000100
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#define EBC0_BNAP_RE_DISABLED 0x00000000
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/* Sample On Ready */
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#define EBC0_BNAP_SOR_DELAYED 0x00000000
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#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
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/* Byte Enable Mode */
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#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
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#define EBC0_BNAP_BEM_RW 0x00000040
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/* Parity Enable */
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#define EBC0_BNAP_PEN_DISABLED 0x00000000
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#define EBC0_BNAP_PEN_ENABLED 0x00000020
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/*----------------------------------------------------------------------------+
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| Define Boot devices
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+----------------------------------------------------------------------------*/
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/* */
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#define BOOT_FROM_SMALL_FLASH 0x00
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#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
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#define BOOT_FROM_NAND_FLASH0 0x02
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#define BOOT_FROM_PCI 0x03
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#define BOOT_DEVICE_UNKNOWN 0x04
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#define PVR_POWERPC_440EP_PASS1 0x42221850
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#define PVR_POWERPC_440EP_PASS2 0x422218D3
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#define TRUE 1
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#define FALSE 0
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#define GPIO0 0
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#define GPIO1 1
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/*#define MAX_SELECTION_NB CORE_NB */
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#define MAX_CORE_SELECT_NB 22
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/*----------------------------------------------------------------------------+
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| PPC440EP GPIOs addresses.
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+----------------------------------------------------------------------------*/
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#define GPIO0_REAL 0xEF600B00
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#define GPIO1_REAL 0xEF600C00
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/* Offsets */
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#define GPIOx_OR 0x00 /* GPIO Output Register */
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#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
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#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
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#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
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#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
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#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
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#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
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#define GPIOx_IR 0x1C /* GPIO Input Register */
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#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
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#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
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#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
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#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
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#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
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#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
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#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
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#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
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#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
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/* GPIO0 */
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#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
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#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
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#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
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#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
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#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
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#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
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/* GPIO1 */
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#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
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#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
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#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
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#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
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#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
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#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
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#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
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#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
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#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
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#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
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#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
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/*----------------------------------------------------------------------------+
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| XX XX
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| XXXXXX XXX XX XXX XXX
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| XX XX X XX XX XX
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| XX XX X XX XX XX
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| XX XX XX XX XX
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| XXXXXX XXX XXX XXXX XXXX
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| Defines
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+----------------------------------------------------------------------------*/
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typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
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ZMII_CONFIGURATION_IS_MII,
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ZMII_CONFIGURATION_IS_RMII,
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ZMII_CONFIGURATION_IS_SMII
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} zmii_config_t;
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/*----------------------------------------------------------------------------+
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| Declare Configuration values
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+----------------------------------------------------------------------------*/
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typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
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typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
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typedef enum config_list { IIC_CORE,
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SCP_CORE,
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DMA_CHANNEL_AB,
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UIC_4_9,
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USB2_HOST,
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DMA_CHANNEL_CD,
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USB2_DEVICE,
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PACKET_REJ_FUNC_AVAIL,
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USB1_DEVICE,
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EBC_MASTER,
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NAND_FLASH,
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UART_CORE0,
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UART_CORE1,
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UART_CORE2,
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UART_CORE3,
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MII_SEL,
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RMII_SEL,
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SMII_SEL,
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PACKET_REJ_FUNC_EN,
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UIC_0_3,
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USB1_HOST,
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PCI_PATCH,
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CORE_NB
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} core_list_t;
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typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
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B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
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B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
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B3_V16, B3_VALUE_UNKNOWN
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} block3_value_t;
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typedef enum config_validity { CONFIG_IS_VALID,
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CONFIG_IS_INVALID
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} config_validity_t;
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