upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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96 lines
2.6 KiB
96 lines
2.6 KiB
/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------- */
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void get_sys_info (sys_info_t * sysInfo)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint plat_ratio,e500_ratio,half_freqSystemBus;
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plat_ratio = (gur->porpllsr) & 0x0000003e;
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plat_ratio >>= 1;
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sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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e500_ratio = (gur->porpllsr) & 0x003f0000;
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e500_ratio >>= 16;
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/* Divide before multiply to avoid integer
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* overflow for processor speeds above 2GHz */
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half_freqSystemBus = sysInfo->freqSystemBus/2;
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sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
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}
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int get_clocks (void)
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{
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sys_info_t sys_info;
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#if defined(CONFIG_CPM2)
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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uint sccr, dfbrg;
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/* set VCO = 4 * BRG */
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immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
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sccr = immap->im_cpm.im_cpm_intctl.sccr;
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dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
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#endif
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get_sys_info (&sys_info);
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gd->cpu_clk = sys_info.freqProcessor;
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gd->bus_clk = sys_info.freqSystemBus;
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#if defined(CONFIG_CPM2)
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gd->vco_out = 2*sys_info.freqSystemBus;
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gd->cpm_clk = gd->vco_out / 2;
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gd->scc_clk = gd->vco_out / 4;
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gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
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#endif
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if(gd->cpu_clk != 0) return (0);
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else return (1);
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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ulong val;
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sys_info_t sys_info;
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get_sys_info (&sys_info);
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val = sys_info.freqSystemBus;
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return val;
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}
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