upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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93 lines
3.0 KiB
93 lines
3.0 KiB
/*
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* Copyright 2006 Freescale Semiconductor.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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/* Config the VIA chip */
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void mpc85xx_config_via(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pci_dev_t bridge;
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unsigned int cmdstat;
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/* Enable USB and IDE functions */
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pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
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cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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/*
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* Force the backplane P2P bridge to have a window
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* open from 0x00000000-0x00001fff in PCI I/O space.
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* This allows legacy I/O (i8259, etc) on the VIA
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* southbridge to be accessed.
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*/
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bridge = PCI_BDF(0,BRIDGE_ID,0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
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pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
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pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
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pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
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}
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/* Function 1, IDE */
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void mpc85xx_config_via_usbide(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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/*
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* Since the P2P window was forced to cover the fixed
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* legacy I/O addresses, it is necessary to manually
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* place the base addresses for the IDE and USB functions
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* within this window.
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*/
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
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}
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/* Function 2, USB ports 0-1 */
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void mpc85xx_config_via_usb(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
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}
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/* Function 3, USB ports 2-3 */
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void mpc85xx_config_via_usb2(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
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}
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/* Function 5, Power Management */
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void mpc85xx_config_via_power(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
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}
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/* Function 6, AC97 Interface */
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void mpc85xx_config_via_ac97(struct pci_controller *hose,
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pci_dev_t dev, struct pci_config_table *tab)
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{
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pciauto_config_device(hose, dev);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
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}
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