upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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40 lines
866 B
40 lines
866 B
/*
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* Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
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*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#define CCI500_BASE 0x5FD00000
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#define CCI500_SLAVE_OFFSET 0x1000
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#define CCI500_SNOOP_CTRL
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#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
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#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
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void cci500_init(unsigned int nr_slaves)
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{
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unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
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int i;
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for (i = 0; i < nr_slaves; i++) {
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void __iomem *base;
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u32 tmp;
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base = ioremap(slave_base, SZ_4K);
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tmp = readl(base);
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tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
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writel(tmp, base);
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iounmap(base);
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slave_base += CCI500_SLAVE_OFFSET;
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}
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}
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