upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
2.2 KiB
87 lines
2.2 KiB
/*
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* (C) Copyright 2008
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* Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
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* mpc512x I/O pin/pad initialization for the ADS5121 board
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/types.h>
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#include <asm/io.h>
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void iopin_initialize(iopin_t *ioregs_init, int len)
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{
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short i, j, p;
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u32 *reg;
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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reg = (u32 *)&(im->io_ctrl);
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if (sizeof(ioregs_init) == 0)
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return;
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for (i = 0; i < len; i++) {
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for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
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p < ioregs_init[i].nr_pins; p++, j++) {
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if (ioregs_init[i].bit_or)
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setbits_be32(reg + j, ioregs_init[i].val);
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else
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out_be32 (reg + j, ioregs_init[i].val);
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}
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}
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return;
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}
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void iopin_initialize_bits(iopin_t *ioregs_init, int len)
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{
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short i, j, p;
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u32 *reg, mask;
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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reg = (u32 *)&(im->io_ctrl);
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/* iterate over table entries */
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for (i = 0; i < len; i++) {
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/* iterate over pins within a table entry */
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for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
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p < ioregs_init[i].nr_pins; p++, j++) {
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if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
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/* replace all settings at once */
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out_be32(reg + j, ioregs_init[i].val);
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} else {
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/*
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* only replace individual parts, but
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* REPLACE them instead of just ORing
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* them in and "inheriting" previously
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* set bits which we don't want
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*/
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mask = 0;
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if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
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mask |= IO_PIN_FMUX(3);
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if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
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mask |= IO_PIN_HOLD(3);
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if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
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mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
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if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
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mask |= IO_PIN_ST(1);
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if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
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mask |= IO_PIN_DS(3);
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/*
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* DON'T do the "mask, then insert"
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* in place on the register, it may
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* break access to external hardware
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* (like boot ROMs) when configuring
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* LPB related pins, while the code to
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* configure the pin is read from this
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* very address region
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*/
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clrsetbits_be32(reg + j, mask,
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ioregs_init[i].val & mask);
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}
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}
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}
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}
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