upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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476 lines
15 KiB
476 lines
15 KiB
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc440.h>
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#include <asm/processor.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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ulong flash_get_size (ulong base, int banknum);
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int board_early_init_f(void)
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{
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u32 sdr0_pfc1, sdr0_pfc2;
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u32 reg;
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/* PLB Write pipelining disabled. Denali Core workaround */
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mtdcr(plb0_acr, 0xDE000000);
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mtdcr(plb1_acr, 0xDE000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
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mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
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mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
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mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
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mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
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/* Trace Pins are disabled. SDR0_PFC0 Register */
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mtsdr(SDR0_PFC0, 0x0);
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/* select Ethernet pins */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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/* SMII via ZMII */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
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SDR0_PFC1_SELECT_CONFIG_6;
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mfsdr(SDR0_PFC2, sdr0_pfc2);
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sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
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SDR0_PFC2_SELECT_CONFIG_6;
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/* enable SPI (SCP) */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
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mtsdr(SDR0_PFC2, sdr0_pfc2);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_PFC4, 0x80000000);
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/* PCI arbiter disabled */
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/* PCI Host Configuration disbaled */
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mfsdr(sdr_pci0, reg);
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reg = 0;
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mtsdr(sdr_pci0, 0x00000000 | reg);
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gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
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return 0;
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}
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/*---------------------------------------------------------------------------+
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| misc_init_r.
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+---------------------------------------------------------------------------*/
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int misc_init_r(void)
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{
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u32 pbcr;
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int size_val = 0;
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u32 reg;
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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/*
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* FLASH stuff...
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*/
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/* Re-do sizing to get full correct info */
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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mfebc(pb0cr, pbcr);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(pb0cr, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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/*
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* USB suff...
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*/
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB0, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB0, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*
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* Clear resets
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*/
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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/*
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* Clear PLB4A0_ACR[WRP]
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* This fix will make the MAL burst disabling patch for the Linux
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* EMAC driver obsolete.
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*/
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reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
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mtdcr(plb4_acr, reg);
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/*
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* Reset Lime controller
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*/
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gpio_write_bit(CFG_GPIO_LIME_S, 1);
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udelay(500);
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gpio_write_bit(CFG_GPIO_LIME_RST, 1);
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/* Lime memory clock adjusted to 133MHz */
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out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
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/* Wait untill time expired. Because of requirements in lime manual */
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udelay(300);
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/* Write lime controller memory parameters */
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out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
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/*
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* Reset PHY's
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*/
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gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
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udelay(100);
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gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: lwmon5");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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#if defined(CFG_DRAM_TEST)
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int testdram(void)
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{
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unsigned long *mem = (unsigned long *)0;
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const unsigned long kend = (1024 / sizeof(unsigned long));
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unsigned long k, n;
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mtmsr(0);
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for (k = 0; k < CFG_MBYTES_SDRAM;
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++k, mem += (1024 / sizeof(unsigned long))) {
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if ((k & 1023) == 0) {
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printf("%3d MB\r", k / 1024);
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}
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memset(mem, 0xaaaaaaaa, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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memset(mem, 0x55555555, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0x55555555) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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}
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printf("SDRAM test passes\n");
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return 0;
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}
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#endif
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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/*-------------------------------------------------------------------------+
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| Set priority for all PLB3 devices to 0.
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| Set PLB3 arbiter to fair mode.
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+-------------------------------------------------------------------------*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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mtdcr(plb3_acr, addr | 0x80000000);
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/*-------------------------------------------------------------------------+
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| Set priority for all PLB4 devices to 0.
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+-------------------------------------------------------------------------*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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mtdcr(plb4_acr, addr);
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/*-------------------------------------------------------------------------+
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| Set Nebula PLB4 arbiter to fair mode.
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+-------------------------------------------------------------------------*/
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/* Segment0 */
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
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mtdcr(plb0_acr, addr);
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/* Segment1 */
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addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
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addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
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addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
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addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
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mtdcr(plb1_acr, addr);
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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* Set up Direct MMIO registers
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*--------------------------------------------------------------------------*/
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/*--------------------------------------------------------------------------+
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| PowerPC440EPX PCI Master configuration.
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| Map one 1Gig range of PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
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out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
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out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
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out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
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out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
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out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
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out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
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out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
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/*--------------------------------------------------------------------------+
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* Set up Configuration registers
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*--------------------------------------------------------------------------*/
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/* Program the board's subsystem id/vendor id */
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pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
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CFG_PCI_SUBSYS_VENDORID);
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pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
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/* Configure command register as bus master */
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pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* 240nS PCI clock */
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pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
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/* No error reporting */
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pci_write_config_word(0, PCI_ERREN, 0);
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pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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unsigned short temp_short;
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/*--------------------------------------------------------------------------+
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| Write the PowerPC440 EP PCI Configuration regs.
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| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
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| Enable PowerPC440 EP to act as a PCI memory target (PTM).
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+--------------------------------------------------------------------------*/
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pci_read_config_word(0, PCI_COMMAND, &temp_short);
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pci_write_config_word(0, PCI_COMMAND,
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temp_short | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
|
|
{
|
|
/* Cactus is always configured as host. */
|
|
return (1);
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
void hw_watchdog_reset(void)
|
|
{
|
|
int val;
|
|
|
|
/*
|
|
* Toggle watchdog output
|
|
*/
|
|
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
|
|
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
|
|
}
|
|
|
|
#ifdef CONFIG_POST
|
|
/*
|
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
|
* Called from board_init_f().
|
|
*/
|
|
int post_hotkeys_pressed(void)
|
|
{
|
|
return (ctrlc());
|
|
}
|
|
#endif
|
|
|