upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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596 lines
13 KiB
596 lines
13 KiB
/*
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* Cirrus Logic EP93xx register definitions.
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*
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* Copyright (C) 2009
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* Matthias Kaehlcke <matthias@kaehlcke.net>
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*
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* Copyright (C) 2006
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* Dominic Rath <Dominic.Rath@gmx.de>
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*
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* Copyright (C) 2004, 2005
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* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
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*
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* Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
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*
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* Copyright (C) 2004 Ray Lehtiniemi
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* Copyright (C) 2003 Cirrus Logic, Inc
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* Copyright (C) 1999 ARM Limited.
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*
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#define EP93XX_AHB_BASE 0x80000000
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#define EP93XX_APB_BASE 0x80800000
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/*
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* 0x80000000 - 0x8000FFFF: DMA
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*/
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#define DMA_OFFSET 0x000000
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#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
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#ifndef __ASSEMBLY__
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struct dma_channel {
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uint32_t control;
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uint32_t interrupt;
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uint32_t ppalloc;
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uint32_t status;
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uint32_t reserved0;
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uint32_t remain;
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uint32_t reserved1[2];
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uint32_t maxcnt0;
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uint32_t base0;
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uint32_t current0;
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uint32_t reserved2;
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uint32_t maxcnt1;
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uint32_t base1;
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uint32_t current1;
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uint32_t reserved3;
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};
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struct dma_regs {
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struct dma_channel m2p_channel_0;
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struct dma_channel m2p_channel_1;
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struct dma_channel m2p_channel_2;
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struct dma_channel m2p_channel_3;
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struct dma_channel m2m_channel_0;
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struct dma_channel m2m_channel_1;
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struct dma_channel reserved0[2];
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struct dma_channel m2p_channel_5;
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struct dma_channel m2p_channel_4;
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struct dma_channel m2p_channel_7;
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struct dma_channel m2p_channel_6;
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struct dma_channel m2p_channel_9;
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struct dma_channel m2p_channel_8;
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uint32_t channel_arbitration;
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uint32_t reserved[15];
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uint32_t global_interrupt;
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};
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#endif
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/*
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* 0x80010000 - 0x8001FFFF: Ethernet MAC
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*/
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#define MAC_OFFSET 0x010000
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#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
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#ifndef __ASSEMBLY__
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struct mac_queue {
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uint32_t badd;
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union { /* deal with half-word aligned registers */
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uint32_t blen;
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union {
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uint16_t filler;
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uint16_t curlen;
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};
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};
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uint32_t curadd;
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};
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struct mac_regs {
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uint32_t rxctl;
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uint32_t txctl;
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uint32_t testctl;
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uint32_t reserved0;
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uint32_t miicmd;
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uint32_t miidata;
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uint32_t miists;
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uint32_t reserved1;
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uint32_t selfctl;
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uint32_t inten;
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uint32_t intstsp;
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uint32_t intstsc;
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uint32_t reserved2[2];
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uint32_t diagad;
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uint32_t diagdata;
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uint32_t gt;
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uint32_t fct;
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uint32_t fcf;
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uint32_t afp;
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union {
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struct {
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uint32_t indad;
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uint32_t indad_upper;
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};
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uint32_t hashtbl;
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};
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uint32_t reserved3[2];
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uint32_t giintsts;
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uint32_t giintmsk;
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uint32_t giintrosts;
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uint32_t giintfrc;
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uint32_t txcollcnt;
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uint32_t rxmissnct;
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uint32_t rxruntcnt;
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uint32_t reserved4;
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uint32_t bmctl;
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uint32_t bmsts;
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uint32_t rxbca;
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uint32_t reserved5;
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struct mac_queue rxdq;
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uint32_t rxdqenq;
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struct mac_queue rxstsq;
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uint32_t rxstsqenq;
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struct mac_queue txdq;
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uint32_t txdqenq;
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struct mac_queue txstsq;
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uint32_t reserved6;
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uint32_t rxbufthrshld;
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uint32_t txbufthrshld;
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uint32_t rxststhrshld;
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uint32_t txststhrshld;
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uint32_t rxdthrshld;
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uint32_t txdthrshld;
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uint32_t maxfrmlen;
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uint32_t maxhdrlen;
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};
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#endif
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#define SELFCTL_RWP (1 << 7)
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#define SELFCTL_GPO0 (1 << 5)
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#define SELFCTL_PUWE (1 << 4)
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#define SELFCTL_PDWE (1 << 3)
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#define SELFCTL_MIIL (1 << 2)
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#define SELFCTL_RESET (1 << 0)
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#define INTSTS_RWI (1 << 30)
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#define INTSTS_RXMI (1 << 29)
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#define INTSTS_RXBI (1 << 28)
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#define INTSTS_RXSQI (1 << 27)
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#define INTSTS_TXLEI (1 << 26)
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#define INTSTS_ECIE (1 << 25)
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#define INTSTS_TXUHI (1 << 24)
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#define INTSTS_MOI (1 << 18)
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#define INTSTS_TXCOI (1 << 17)
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#define INTSTS_RXROI (1 << 16)
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#define INTSTS_MIII (1 << 12)
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#define INTSTS_PHYI (1 << 11)
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#define INTSTS_TI (1 << 10)
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#define INTSTS_AHBE (1 << 8)
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#define INTSTS_OTHER (1 << 4)
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#define INTSTS_TXSQ (1 << 3)
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#define INTSTS_RXSQ (1 << 2)
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#define BMCTL_MT (1 << 13)
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#define BMCTL_TT (1 << 12)
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#define BMCTL_UNH (1 << 11)
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#define BMCTL_TXCHR (1 << 10)
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#define BMCTL_TXDIS (1 << 9)
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#define BMCTL_TXEN (1 << 8)
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#define BMCTL_EH2 (1 << 6)
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#define BMCTL_EH1 (1 << 5)
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#define BMCTL_EEOB (1 << 4)
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#define BMCTL_RXCHR (1 << 2)
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#define BMCTL_RXDIS (1 << 1)
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#define BMCTL_RXEN (1 << 0)
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#define BMSTS_TXACT (1 << 7)
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#define BMSTS_TP (1 << 4)
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#define BMSTS_RXACT (1 << 3)
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#define BMSTS_QID_MASK 0x07
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#define BMSTS_QID_RXDATA 0x00
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#define BMSTS_QID_TXDATA 0x01
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#define BMSTS_QID_RXSTS 0x02
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#define BMSTS_QID_TXSTS 0x03
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#define BMSTS_QID_RXDESC 0x04
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#define BMSTS_QID_TXDESC 0x05
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#define AFP_MASK 0x07
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#define AFP_IAPRIMARY 0x00
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#define AFP_IASECONDARY1 0x01
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#define AFP_IASECONDARY2 0x02
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#define AFP_IASECONDARY3 0x03
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#define AFP_TX 0x06
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#define AFP_HASH 0x07
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#define RXCTL_PAUSEA (1 << 20)
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#define RXCTL_RXFCE1 (1 << 19)
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#define RXCTL_RXFCE0 (1 << 18)
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#define RXCTL_BCRC (1 << 17)
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#define RXCTL_SRXON (1 << 16)
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#define RXCTL_RCRCA (1 << 13)
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#define RXCTL_RA (1 << 12)
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#define RXCTL_PA (1 << 11)
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#define RXCTL_BA (1 << 10)
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#define RXCTL_MA (1 << 9)
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#define RXCTL_IAHA (1 << 8)
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#define RXCTL_IA3 (1 << 3)
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#define RXCTL_IA2 (1 << 2)
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#define RXCTL_IA1 (1 << 1)
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#define RXCTL_IA0 (1 << 0)
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#define TXCTL_DEFDIS (1 << 7)
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#define TXCTL_MBE (1 << 6)
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#define TXCTL_ICRC (1 << 5)
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#define TXCTL_TPD (1 << 4)
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#define TXCTL_OCOLL (1 << 3)
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#define TXCTL_SP (1 << 2)
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#define TXCTL_PB (1 << 1)
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#define TXCTL_STXON (1 << 0)
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#define MIICMD_REGAD_MASK (0x001F)
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#define MIICMD_PHYAD_MASK (0x03E0)
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#define MIICMD_OPCODE_MASK (0xC000)
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#define MIICMD_PHYAD_8950 (0x0000)
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#define MIICMD_OPCODE_READ (0x8000)
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#define MIICMD_OPCODE_WRITE (0x4000)
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#define MIISTS_BUSY (1 << 0)
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/*
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* 0x80020000 - 0x8002FFFF: USB OHCI
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*/
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#define USB_OFFSET 0x020000
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#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
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/*
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* 0x80030000 - 0x8003FFFF: Raster engine
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*/
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#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
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#define RASTER_OFFSET 0x030000
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#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
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#endif
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/*
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* 0x80040000 - 0x8004FFFF: Graphics accelerator
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*/
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#if defined(CONFIG_EP9315)
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#define GFX_OFFSET 0x040000
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#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
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#endif
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/*
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* 0x80050000 - 0x8005FFFF: Reserved
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*/
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/*
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* 0x80060000 - 0x8006FFFF: SDRAM controller
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*/
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#define SDRAM_OFFSET 0x060000
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#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
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#ifndef __ASSEMBLY__
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struct sdram_regs {
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uint32_t reserved;
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uint32_t glconfig;
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uint32_t refrshtimr;
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uint32_t bootsts;
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uint32_t devcfg0;
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uint32_t devcfg1;
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uint32_t devcfg2;
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uint32_t devcfg3;
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};
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#endif
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#define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
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#define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
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#define SDRAM_DEVCFG_SROMLL (1 << 5)
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#define SDRAM_DEVCFG_CASLAT_2 0x00010000
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#define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
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#define GLCONFIG_INIT (1 << 0)
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#define GLCONFIG_MRS (1 << 1)
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#define GLCONFIG_SMEMBUSY (1 << 5)
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#define GLCONFIG_LCR (1 << 6)
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#define GLCONFIG_REARBEN (1 << 7)
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#define GLCONFIG_CLKSHUTDOWN (1 << 30)
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#define GLCONFIG_CKE (1 << 31)
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/*
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* 0x80070000 - 0x8007FFFF: Reserved
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*/
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/*
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* 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
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*/
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#define SMC_OFFSET 0x080000
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#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
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#ifndef __ASSEMBLY__
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struct smc_regs {
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uint32_t bcr0;
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uint32_t bcr1;
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uint32_t bcr2;
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uint32_t bcr3;
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uint32_t reserved0[2];
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uint32_t bcr6;
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uint32_t bcr7;
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#if defined(CONFIG_EP9315)
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uint32_t pcattribute;
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uint32_t pccommon;
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uint32_t pcio;
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uint32_t reserved1[5];
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uint32_t pcmciactrl;
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#endif
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};
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#endif
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#define SMC_BCR_IDCY_SHIFT 0
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#define SMC_BCR_WST1_SHIFT 5
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#define SMC_BCR_BLE (1 << 10)
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#define SMC_BCR_WST2_SHIFT 11
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#define SMC_BCR_MW_SHIFT 28
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/*
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* 0x80090000 - 0x8009FFFF: Boot ROM
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*/
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/*
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* 0x800A0000 - 0x800AFFFF: IDE interface
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*/
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/*
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* 0x800B0000 - 0x800BFFFF: VIC1
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*/
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/*
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* 0x800C0000 - 0x800CFFFF: VIC2
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*/
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/*
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* 0x800D0000 - 0x800FFFFF: Reserved
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*/
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/*
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* 0x80800000 - 0x8080FFFF: Reserved
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*/
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/*
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* 0x80810000 - 0x8081FFFF: Timers
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*/
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#define TIMER_OFFSET 0x010000
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#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
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#ifndef __ASSEMBLY__
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struct timer {
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uint32_t load;
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uint32_t value;
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uint32_t control;
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uint32_t clear;
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};
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struct timer4 {
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uint32_t value_low;
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uint32_t value_high;
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};
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struct timer_regs {
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struct timer timer1;
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uint32_t reserved0[4];
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struct timer timer2;
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uint32_t reserved1[12];
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struct timer4 timer4;
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uint32_t reserved2[6];
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struct timer timer3;
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};
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#endif
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/*
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* 0x80820000 - 0x8082FFFF: I2S
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*/
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#define I2S_OFFSET 0x020000
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#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
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/*
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* 0x80830000 - 0x8083FFFF: Security
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*/
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#define SECURITY_OFFSET 0x030000
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#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
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#define EXTENSIONID (SECURITY_BASE + 0x2714)
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/*
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* 0x80840000 - 0x8084FFFF: GPIO
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*/
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#define GPIO_OFFSET 0x040000
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#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
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#ifndef __ASSEMBLY__
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struct gpio_int {
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uint32_t inttype1;
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uint32_t inttype2;
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uint32_t eoi;
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uint32_t inten;
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uint32_t intsts;
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uint32_t rawintsts;
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uint32_t db;
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};
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struct gpio_regs {
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uint32_t padr;
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uint32_t pbdr;
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uint32_t pcdr;
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uint32_t pddr;
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uint32_t paddr;
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uint32_t pbddr;
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uint32_t pcddr;
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uint32_t pdddr;
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uint32_t pedr;
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uint32_t peddr;
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uint32_t reserved0[2];
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uint32_t pfdr;
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uint32_t pfddr;
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uint32_t pgdr;
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uint32_t pgddr;
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uint32_t phdr;
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uint32_t phddr;
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uint32_t reserved1;
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uint32_t finttype1;
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uint32_t finttype2;
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uint32_t reserved2;
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struct gpio_int pfint;
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uint32_t reserved3[10];
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struct gpio_int paint;
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struct gpio_int pbint;
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uint32_t eedrive;
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};
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#endif
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/*
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* 0x80850000 - 0x8087FFFF: Reserved
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*/
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/*
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* 0x80880000 - 0x8088FFFF: AAC
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*/
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#define AAC_OFFSET 0x080000
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#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
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/*
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* 0x80890000 - 0x8089FFFF: Reserved
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*/
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/*
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* 0x808A0000 - 0x808AFFFF: SPI
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*/
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#define SPI_OFFSET 0x0A0000
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#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
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/*
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* 0x808B0000 - 0x808BFFFF: IrDA
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*/
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#define IRDA_OFFSET 0x0B0000
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#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
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/*
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* 0x808C0000 - 0x808CFFFF: UART1
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*/
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#define UART1_OFFSET 0x0C0000
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#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
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/*
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* 0x808D0000 - 0x808DFFFF: UART2
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*/
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#define UART2_OFFSET 0x0D0000
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#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
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/*
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* 0x808E0000 - 0x808EFFFF: UART3
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*/
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#define UART3_OFFSET 0x0E0000
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#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
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/*
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* 0x808F0000 - 0x808FFFFF: Key Matrix
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*/
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#define KEY_OFFSET 0x0F0000
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#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
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/*
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* 0x80900000 - 0x8090FFFF: Touchscreen
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*/
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#define TOUCH_OFFSET 0x900000
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#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
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/*
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* 0x80910000 - 0x8091FFFF: Pulse Width Modulation
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*/
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#define PWM_OFFSET 0x910000
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#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
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/*
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* 0x80920000 - 0x8092FFFF: Real time clock
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*/
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#define RTC_OFFSET 0x920000
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#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
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/*
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* 0x80930000 - 0x8093FFFF: Syscon
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*/
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#define SYSCON_OFFSET 0x930000
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#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
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#ifndef __ASSEMBLY__
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struct syscon_regs {
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uint32_t pwrsts;
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uint32_t pwrcnt;
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uint32_t halt;
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uint32_t stby;
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uint32_t reserved0[2];
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uint32_t teoi;
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uint32_t stfclr;
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uint32_t clkset1;
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uint32_t clkset2;
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uint32_t reserved1[6];
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uint32_t scratch0;
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uint32_t scratch1;
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uint32_t reserved2[2];
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uint32_t apbwait;
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uint32_t bustmstrarb;
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uint32_t bootmodeclr;
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uint32_t reserved3[9];
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uint32_t devicecfg;
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uint32_t vidclkdiv;
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uint32_t mirclkdiv;
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uint32_t i2sclkdiv;
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uint32_t keytchclkdiv;
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uint32_t chipid;
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uint32_t reserved4;
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uint32_t syscfg;
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uint32_t reserved5[8];
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uint32_t sysswlock;
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};
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#else
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#define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
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#endif
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#define SYSCON_PWRCNT_UART_BAUD (1 << 29)
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#define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
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#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
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#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
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#define SYSCON_CLKSET_PLL_PS_SHIFT 16
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#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
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#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
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#define SYSCON_CLKSET1_NBYP1 (1 << 23)
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#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
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#define SYSCON_CLKSET2_PLL2_EN (1 << 18)
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#define SYSCON_CLKSET2_NBYP2 (1 << 19)
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#define SYSCON_CLKSET2_USB_DIV_SHIFT 28
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#define SYSCON_CHIPID_REV_MASK 0xF0000000
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#define SYSCON_DEVICECFG_SWRST (1 << 31)
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/*
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* 0x80930000 - 0x8093FFFF: Watchdog Timer
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*/
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#define WATCHDOG_OFFSET 0x940000
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#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
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/*
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* 0x80950000 - 0x9000FFFF: Reserved
|
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*/
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