upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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494 lines
15 KiB
494 lines
15 KiB
/*
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* Altera 10/100/1000 triple speed ethernet mac
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*
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* Copyright (C) 2008 Altera Corporation.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ALTERA_TSE_H_
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#define _ALTERA_TSE_H_
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#define __packed_1_ __attribute__ ((packed, aligned(1)))
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/* PHY Stuff */
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#define miim_end -2
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#define miim_read -1
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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#define MIIMCFG_INIT_VALUE 0x00000003
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#define MIIMCFG_RESET 0x80000000
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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#define MIIM_CONTROL 0x00
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#define MIIM_CONTROL_RESET 0x00009140
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#define MIIM_CONTROL_INIT 0x00001140
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#define MIIM_CONTROL_RESTART 0x00001340
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#define MIIM_ANEN 0x00001000
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#define MIIM_CR 0x00
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#define MIIM_CR_RST 0x00008000
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#define MIIM_CR_INIT 0x00001000
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#define MIIM_STATUS 0x1
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#define MIIM_STATUS_AN_DONE 0x00000020
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#define MIIM_STATUS_LINK 0x0004
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#define PHY_BMSR_AUTN_ABLE 0x0008
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#define PHY_BMSR_AUTN_COMP 0x0020
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#define MIIM_PHYIR1 0x2
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#define MIIM_PHYIR2 0x3
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#define MIIM_ANAR 0x4
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#define MIIM_ANAR_INIT 0x1e1
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#define MIIM_TBI_ANLPBPA 0x5
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#define MIIM_TBI_ANLPBPA_HALF 0x00000040
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#define MIIM_TBI_ANLPBPA_FULL 0x00000020
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#define MIIM_TBI_ANEX 0x6
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#define MIIM_TBI_ANEX_NP 0x00000004
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#define MIIM_TBI_ANEX_PRX 0x00000002
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#define MIIM_GBIT_CONTROL 0x9
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#define MIIM_GBIT_CONTROL_INIT 0xe00
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#define MIIM_EXT_PAGE_ACCESS 0x1f
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/* 88E1011 PHY Status Register */
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#define MIIM_88E1011_PHY_STATUS 0x11
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#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
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#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
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#define MIIM_88E1011_PHYSTAT_100 0x4000
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#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
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#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
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#define MIIM_88E1011_PHYSTAT_LINK 0x0400
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#define MIIM_88E1011_PHY_SCR 0x10
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#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
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#define MIIM_88E1111_PHY_EXT_CR 0x14
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#define MIIM_88E1111_PHY_EXT_SR 0x1b
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/* 88E1111 PHY LED Control Register */
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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#define MIIM_READ_COMMAND 0x00000001
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/* struct phy_info: a structure which defines attributes for a PHY
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* id will contain a number which represents the PHY. During
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* startup, the driver will poll the PHY to find out what its
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* UID--as defined by registers 2 and 3--is. The 32-bit result
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* gotten from the PHY will be shifted right by "shift" bits to
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* discard any bits which may change based on revision numbers
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* unimportant to functionality
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*
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* The struct phy_cmd entries represent pointers to an arrays of
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* commands which tell the driver what to do to the PHY.
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*/
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struct phy_info {
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uint id;
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char *name;
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uint shift;
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/* Called to configure the PHY, and modify the controller
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* based on the results */
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struct phy_cmd *config;
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/* Called when starting up the controller */
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struct phy_cmd *startup;
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/* Called when bringing down the controller */
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struct phy_cmd *shutdown;
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};
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/* SGDMA Stuff */
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#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
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#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
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#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004)
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#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
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#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
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#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001)
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#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002)
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#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004)
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#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008)
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#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010)
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#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
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#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080)
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#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00)
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
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#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000)
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#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000)
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#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
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| ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
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| ALT_SGDMA_CONTROL_IE_GLOBAL_MSK)
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/*
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* Descriptor control bit masks & offsets
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*
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* Note: The control byte physically occupies bits [31:24] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the control register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
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/*
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* Descriptor status bit masks & offsets
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*
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* Note: The status byte physically occupies bits [23:16] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the status register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F)
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/*
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* The SGDMA controller buffer descriptor allocates
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* 64 bits for each address. To support ANSI C, the
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* struct implementing a descriptor places 32-bits
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* of padding directly above each address; each pad must
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* be cleared when initializing a descriptor.
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*/
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/*
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* Buffer Descriptor data structure
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*
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*/
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struct alt_sgdma_descriptor {
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unsigned int *source; /* the address of data to be read. */
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unsigned int source_pad;
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unsigned int *destination; /* the address to write data */
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unsigned int destination_pad;
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unsigned int *next; /* the next descriptor in the list. */
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unsigned int next_pad;
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unsigned short bytes_to_transfer; /* the number of bytes to transfer */
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unsigned char read_burst;
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unsigned char write_burst;
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unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
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unsigned char descriptor_status;
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unsigned char descriptor_control;
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} __packed_1_;
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/* SG-DMA Control/Status Slave registers map */
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struct alt_sgdma_registers {
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unsigned int status;
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unsigned int status_pad[3];
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unsigned int control;
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unsigned int control_pad[3];
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unsigned int next_descriptor_pointer;
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unsigned int descriptor_pad[3];
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};
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/* TSE Stuff */
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#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
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#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
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#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004)
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#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
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#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010)
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#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020)
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#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040)
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#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080)
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#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100)
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#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200)
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#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
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#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800)
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#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000)
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#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
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#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000)
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#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000)
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/* Bits (18:16) = address select */
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#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000)
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#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000)
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#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000)
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#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000)
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#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000)
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#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000)
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#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000)
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#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
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#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000)
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/* Bits (30..27) reserved */
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#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000)
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#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000)
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#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000)
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#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
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#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000
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#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000
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/* Command_Config Register Bit Definitions */
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typedef volatile union __alt_tse_command_config {
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unsigned int image;
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struct {
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unsigned int
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transmit_enable:1, /* bit 0 */
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receive_enable:1, /* bit 1 */
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pause_frame_xon_gen:1, /* bit 2 */
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ethernet_speed:1, /* bit 3 */
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promiscuous_enable:1, /* bit 4 */
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pad_enable:1, /* bit 5 */
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crc_forward:1, /* bit 6 */
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pause_frame_forward:1, /* bit 7 */
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pause_frame_ignore:1, /* bit 8 */
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set_mac_address_on_tx:1, /* bit 9 */
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halfduplex_enable:1, /* bit 10 */
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excessive_collision:1, /* bit 11 */
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late_collision:1, /* bit 12 */
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software_reset:1, /* bit 13 */
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multicast_hash_mode_sel:1, /* bit 14 */
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loopback_enable:1, /* bit 15 */
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src_mac_addr_sel_on_tx:3, /* bit 18:16 */
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magic_packet_detect:1, /* bit 19 */
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sleep_mode_enable:1, /* bit 20 */
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wake_up_request:1, /* bit 21 */
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pause_frame_xoff_gen:1, /* bit 22 */
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control_frame_enable:1, /* bit 23 */
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payload_len_chk_disable:1, /* bit 24 */
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enable_10mbps_intf:1, /* bit 25 */
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rx_error_discard_enable:1, /* bit 26 */
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reserved_bits:4, /* bit 30:27 */
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self_clear_counter_reset:1; /* bit 31 */
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} __packed_1_ bits;
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} __packed_1_ alt_tse_command_config;
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/* Tx_Cmd_Stat Register Bit Definitions */
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typedef volatile union __alt_tse_tx_cmd_stat {
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unsigned int image;
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struct {
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unsigned int reserved_lsbs:17, /* bit 16:0 */
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omit_crc:1, /* bit 17 */
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tx_shift16:1, /* bit 18 */
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reserved_msbs:13; /* bit 31:19 */
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} __packed_1_ bits;
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} alt_tse_tx_cmd_stat;
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/* Rx_Cmd_Stat Register Bit Definitions */
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typedef volatile union __alt_tse_rx_cmd_stat {
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unsigned int image;
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struct {
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unsigned int reserved_lsbs:25, /* bit 24:0 */
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rx_shift16:1, /* bit 25 */
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reserved_msbs:6; /* bit 31:26 */
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} __packed_1_ bits;
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} alt_tse_rx_cmd_stat;
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struct alt_tse_mdio {
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unsigned int control; /*PHY device operation control register */
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unsigned int status; /*PHY device operation status register */
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unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */
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unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */
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unsigned int auto_negotiation_advertisement;
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unsigned int remote_partner_base_page_ability;
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unsigned int reg6;
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unsigned int reg7;
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unsigned int reg8;
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unsigned int reg9;
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unsigned int rega;
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unsigned int regb;
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unsigned int regc;
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unsigned int regd;
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unsigned int rege;
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unsigned int regf;
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unsigned int reg10;
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unsigned int reg11;
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unsigned int reg12;
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unsigned int reg13;
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unsigned int reg14;
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unsigned int reg15;
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unsigned int reg16;
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unsigned int reg17;
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unsigned int reg18;
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unsigned int reg19;
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unsigned int reg1a;
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unsigned int reg1b;
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unsigned int reg1c;
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unsigned int reg1d;
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unsigned int reg1e;
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unsigned int reg1f;
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};
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/* MAC register Space */
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struct alt_tse_mac {
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unsigned int megacore_revision;
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unsigned int scratch_pad;
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alt_tse_command_config command_config;
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unsigned int mac_addr_0;
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unsigned int mac_addr_1;
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unsigned int max_frame_length;
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unsigned int pause_quanta;
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unsigned int rx_sel_empty_threshold;
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unsigned int rx_sel_full_threshold;
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unsigned int tx_sel_empty_threshold;
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unsigned int tx_sel_full_threshold;
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unsigned int rx_almost_empty_threshold;
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unsigned int rx_almost_full_threshold;
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unsigned int tx_almost_empty_threshold;
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unsigned int tx_almost_full_threshold;
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unsigned int mdio_phy0_addr;
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unsigned int mdio_phy1_addr;
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/* only if 100/1000 BaseX PCS, reserved otherwise */
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unsigned int reservedx44[5];
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unsigned int reg_read_access_status;
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unsigned int min_tx_ipg_length;
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/* IEEE 802.3 oEntity Managed Object Support */
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unsigned int aMACID_1; /*The MAC addresses */
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unsigned int aMACID_2;
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unsigned int aFramesTransmittedOK;
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unsigned int aFramesReceivedOK;
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unsigned int aFramesCheckSequenceErrors;
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unsigned int aAlignmentErrors;
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unsigned int aOctetsTransmittedOK;
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unsigned int aOctetsReceivedOK;
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/* IEEE 802.3 oPausedEntity Managed Object Support */
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unsigned int aTxPAUSEMACCtrlFrames;
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unsigned int aRxPAUSEMACCtrlFrames;
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/* IETF MIB (MIB-II) Object Support */
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unsigned int ifInErrors;
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unsigned int ifOutErrors;
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unsigned int ifInUcastPkts;
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unsigned int ifInMulticastPkts;
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unsigned int ifInBroadcastPkts;
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unsigned int ifOutDiscards;
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unsigned int ifOutUcastPkts;
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unsigned int ifOutMulticastPkts;
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unsigned int ifOutBroadcastPkts;
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/* IETF RMON MIB Object Support */
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unsigned int etherStatsDropEvent;
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unsigned int etherStatsOctets;
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unsigned int etherStatsPkts;
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unsigned int etherStatsUndersizePkts;
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unsigned int etherStatsOversizePkts;
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unsigned int etherStatsPkts64Octets;
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unsigned int etherStatsPkts65to127Octets;
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unsigned int etherStatsPkts128to255Octets;
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unsigned int etherStatsPkts256to511Octets;
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unsigned int etherStatsPkts512to1023Octets;
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unsigned int etherStatsPkts1024to1518Octets;
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unsigned int etherStatsPkts1519toXOctets;
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unsigned int etherStatsJabbers;
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unsigned int etherStatsFragments;
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unsigned int reservedxE4;
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/*FIFO control register. */
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alt_tse_tx_cmd_stat tx_cmd_stat;
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alt_tse_rx_cmd_stat rx_cmd_stat;
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unsigned int ipaccTxConf;
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unsigned int ipaccRxConf;
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unsigned int ipaccRxStat;
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unsigned int ipaccRxStatSum;
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/*Multicast address resolution table */
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unsigned int hash_table[64];
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/*Registers 0 to 31 within PHY device 0/1 */
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struct alt_tse_mdio mdio_phy0;
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struct alt_tse_mdio mdio_phy1;
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/*4 Supplemental MAC Addresses */
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unsigned int supp_mac_addr_0_0;
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unsigned int supp_mac_addr_0_1;
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unsigned int supp_mac_addr_1_0;
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unsigned int supp_mac_addr_1_1;
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|
unsigned int supp_mac_addr_2_0;
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|
unsigned int supp_mac_addr_2_1;
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|
unsigned int supp_mac_addr_3_0;
|
|
unsigned int supp_mac_addr_3_1;
|
|
|
|
unsigned int reservedx320[56];
|
|
};
|
|
|
|
/* flags: TSE MII modes */
|
|
/* GMII/MII = 0 */
|
|
/* RGMII = 1 */
|
|
/* RGMII_ID = 2 */
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|
/* RGMII_TXID = 3 */
|
|
/* RGMII_RXID = 4 */
|
|
/* SGMII = 5 */
|
|
struct altera_tse_priv {
|
|
char devname[16];
|
|
volatile struct alt_tse_mac *mac_dev;
|
|
volatile struct alt_sgdma_registers *sgdma_rx;
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|
volatile struct alt_sgdma_registers *sgdma_tx;
|
|
unsigned int rx_sgdma_irq;
|
|
unsigned int tx_sgdma_irq;
|
|
unsigned int has_descriptor_mem;
|
|
unsigned int descriptor_mem_base;
|
|
unsigned int descriptor_mem_size;
|
|
volatile struct alt_sgdma_descriptor *rx_desc;
|
|
volatile struct alt_sgdma_descriptor *tx_desc;
|
|
volatile unsigned char *rx_buf;
|
|
struct phy_info *phyinfo;
|
|
unsigned int phyaddr;
|
|
unsigned int flags;
|
|
unsigned int link;
|
|
unsigned int duplexity;
|
|
unsigned int speed;
|
|
};
|
|
|
|
/* Phy stuff continued */
|
|
/*
|
|
* struct phy_cmd: A command for reading or writing a PHY register
|
|
*
|
|
* mii_reg: The register to read or write
|
|
*
|
|
* mii_data: For writes, the value to put in the register.
|
|
* A value of -1 indicates this is a read.
|
|
*
|
|
* funct: A function pointer which is invoked for each command.
|
|
* For reads, this function will be passed the value read
|
|
* from the PHY, and process it.
|
|
* For writes, the result of this function will be written
|
|
* to the PHY register
|
|
*/
|
|
struct phy_cmd {
|
|
uint mii_reg;
|
|
uint mii_data;
|
|
uint(*funct) (uint mii_reg, struct altera_tse_priv *priv);
|
|
};
|
|
#endif /* _ALTERA_TSE_H_ */
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|
|