upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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283 lines
6.8 KiB
283 lines
6.8 KiB
/*
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* board/renesas/koelsch/koelsch.c
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <i2c.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define s_init_wait(cnt) \
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({ \
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u32 i = 0x10000 * cnt; \
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while (i > 0) \
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i--; \
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})
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#define dbpdrgd_check(bsc) \
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({ \
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while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
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; \
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})
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#if defined(CONFIG_NORFLASH)
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static void bsc_init(void)
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{
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struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
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struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
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/* LBSC */
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writel(0x00000020, &lbsc->cs0ctrl);
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writel(0x00000020, &lbsc->cs1ctrl);
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writel(0x00002020, &lbsc->ecs0ctrl);
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writel(0x00002020, &lbsc->ecs1ctrl);
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writel(0x077F077F, &lbsc->cswcr0);
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writel(0x077F077F, &lbsc->cswcr1);
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writel(0x077F077F, &lbsc->ecswcr0);
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writel(0x077F077F, &lbsc->ecswcr1);
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/* DBSC3 */
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s_init_wait(10);
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writel(0x0000A55A, &dbsc3_0->dbpdlck);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x80000000, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000006, &dbsc3_0->dbpdrga);
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writel(0x0001C000, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FD2480, &dbsc3_0->dbpdrgd);
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writel(0x00000010, &dbsc3_0->dbpdrga);
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writel(0xF004649B, &dbsc3_0->dbpdrgd);
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writel(0x0000000F, &dbsc3_0->dbpdrga);
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writel(0x00181EE4, &dbsc3_0->dbpdrgd);
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writel(0x0000000E, &dbsc3_0->dbpdrga);
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writel(0x33C03812, &dbsc3_0->dbpdrgd);
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writel(0x00000003, &dbsc3_0->dbpdrga);
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writel(0x0300C481, &dbsc3_0->dbpdrgd);
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writel(0x00000007, &dbsc3_0->dbkind);
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writel(0x10030A02, &dbsc3_0->dbconf0);
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writel(0x00000001, &dbsc3_0->dbphytype);
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writel(0x00000000, &dbsc3_0->dbbl);
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writel(0x0000000B, &dbsc3_0->dbtr0);
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writel(0x00000008, &dbsc3_0->dbtr1);
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writel(0x00000000, &dbsc3_0->dbtr2);
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writel(0x0000000B, &dbsc3_0->dbtr3);
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writel(0x000C000B, &dbsc3_0->dbtr4);
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writel(0x00000027, &dbsc3_0->dbtr5);
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writel(0x0000001C, &dbsc3_0->dbtr6);
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writel(0x00000005, &dbsc3_0->dbtr7);
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writel(0x00000018, &dbsc3_0->dbtr8);
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writel(0x00000008, &dbsc3_0->dbtr9);
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writel(0x0000000C, &dbsc3_0->dbtr10);
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writel(0x00000009, &dbsc3_0->dbtr11);
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writel(0x00000012, &dbsc3_0->dbtr12);
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writel(0x000000D0, &dbsc3_0->dbtr13);
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writel(0x00140005, &dbsc3_0->dbtr14);
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writel(0x00050004, &dbsc3_0->dbtr15);
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writel(0x70233005, &dbsc3_0->dbtr16);
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writel(0x000C0000, &dbsc3_0->dbtr17);
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writel(0x00000300, &dbsc3_0->dbtr18);
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writel(0x00000040, &dbsc3_0->dbtr19);
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writel(0x00000001, &dbsc3_0->dbrnk0);
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writel(0x00020001, &dbsc3_0->dbadj0);
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writel(0x20082008, &dbsc3_0->dbadj2);
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writel(0x00020002, &dbsc3_0->dbwt0cnf0);
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writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
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writel(0x00000015, &dbsc3_0->dbpdrga);
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writel(0x00000D70, &dbsc3_0->dbpdrgd);
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writel(0x00000016, &dbsc3_0->dbpdrga);
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writel(0x00000006, &dbsc3_0->dbpdrgd);
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writel(0x00000017, &dbsc3_0->dbpdrga);
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writel(0x00000018, &dbsc3_0->dbpdrgd);
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writel(0x00000012, &dbsc3_0->dbpdrga);
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writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
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writel(0x00000013, &dbsc3_0->dbpdrga);
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writel(0x1A868300, &dbsc3_0->dbpdrgd);
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writel(0x00000023, &dbsc3_0->dbpdrga);
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writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
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writel(0x00000014, &dbsc3_0->dbpdrga);
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writel(0x300214D8, &dbsc3_0->dbpdrgd);
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writel(0x0000001A, &dbsc3_0->dbpdrga);
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writel(0x930035C7, &dbsc3_0->dbpdrgd);
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writel(0x00000060, &dbsc3_0->dbpdrga);
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writel(0x330657B2, &dbsc3_0->dbpdrgd);
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writel(0x00000011, &dbsc3_0->dbpdrga);
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writel(0x1000040B, &dbsc3_0->dbpdrgd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000071, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x2100FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x0000FA00, &dbsc3_0->dbcmd);
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writel(0x110000DB, &dbsc3_0->dbcmd);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x00000181, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000001, &dbsc3_0->dbpdrga);
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writel(0x0000FE01, &dbsc3_0->dbpdrgd);
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writel(0x00000004, &dbsc3_0->dbpdrga);
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dbpdrgd_check(dbsc3_0);
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writel(0x00000000, &dbsc3_0->dbbs0cnt1);
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writel(0x01004C20, &dbsc3_0->dbcalcnf);
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writel(0x014000AA, &dbsc3_0->dbcaltr);
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writel(0x00000140, &dbsc3_0->dbrfcnf0);
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writel(0x00081860, &dbsc3_0->dbrfcnf1);
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writel(0x00010000, &dbsc3_0->dbrfcnf2);
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writel(0x00000001, &dbsc3_0->dbrfen);
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writel(0x00000001, &dbsc3_0->dbacen);
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}
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#else
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#define bsc_init() do {} while (0)
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#endif /* CONFIG_NORFLASH */
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void s_init(void)
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{
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struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
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struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* QoS */
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qos_init();
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/* BSC */
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bsc_init();
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}
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#define MSTPSR1 0xE6150038
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#define SMSTPCR1 0xE6150134
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#define TMU0_MSTP125 (1 << 25)
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#define MSTPSR7 0xE61501C4
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#define SMSTPCR7 0xE615014C
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#define SCIF0_MSTP721 (1 << 21)
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#define PMMR 0xE6060000
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#define GPSR4 0xE6060014
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#define IPSR14 0xE6060058
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#define set_guard_reg(addr, mask, value) \
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{ \
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u32 val; \
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val = (readl(addr) & ~(mask)) | (value); \
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writel(~val, PMMR); \
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writel(val, addr); \
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}
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
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out_##type((saddr), in_##type(addr) & ~(clear))
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#define mstp_setbits_le32(addr, saddr, set) \
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mstp_setbits(le32, addr, saddr, set)
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#define mstp_clrbits_le32(addr, saddr, clear) \
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mstp_clrbits(le32, addr, saddr, clear)
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int board_early_init_f(void)
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{
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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#if defined(CONFIG_NORFLASH)
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/* SCIF0 */
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set_guard_reg(GPSR4, 0x34000000, 0x00000000);
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set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
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set_guard_reg(GPSR4, 0x00000000, 0x34000000);
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#endif
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7791_pinmux_init();
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RMOBILE_BOARD_STRING
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};
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
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gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
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}
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int board_late_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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