upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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242 lines
6.3 KiB
242 lines
6.3 KiB
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARC_IO_H
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#define __ASM_ARC_IO_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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/*
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* Given a physical address and a length, return a virtual address
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* that can be used to access the memory range with the caching
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* properties specified by "flags".
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*/
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#define MAP_NOCACHE (0)
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#define MAP_WRCOMBINE (0)
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#define MAP_WRBACK (0)
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#define MAP_WRTHROUGH (0)
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static inline void *
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map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
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{
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return (void *)((unsigned long)paddr);
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}
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/*
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* Take down a mapping set up by map_physmem().
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*/
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static inline void unmap_physmem(void *vaddr, unsigned long flags)
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{
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}
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static inline void sync(void)
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{
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/* Not yet implemented */
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}
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 b;
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__asm__ __volatile__("ldb%U1 %0, %1\n"
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: "=r" (b)
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: "m" (*(volatile u8 __force *)addr)
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: "memory");
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return b;
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}
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 s;
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__asm__ __volatile__("ldw%U1 %0, %1\n"
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: "=r" (s)
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: "m" (*(volatile u16 __force *)addr)
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: "memory");
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return s;
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}
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 w;
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__asm__ __volatile__("ld%U1 %0, %1\n"
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: "=r" (w)
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: "m" (*(volatile u32 __force *)addr)
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: "memory");
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return w;
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}
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#define readb __raw_readb
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static inline u16 readw(const volatile void __iomem *addr)
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{
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return __le16_to_cpu(__raw_readw(addr));
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}
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static inline u32 readl(const volatile void __iomem *addr)
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{
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return __le32_to_cpu(__raw_readl(addr));
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}
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static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stb%U1 %0, %1\n"
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:
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: "r" (b), "m" (*(volatile u8 __force *)addr)
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: "memory");
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}
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static inline void __raw_writew(u16 s, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stw%U1 %0, %1\n"
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:
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: "r" (s), "m" (*(volatile u16 __force *)addr)
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: "memory");
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}
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static inline void __raw_writel(u32 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("st%U1 %0, %1\n"
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:
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: "r" (w), "m" (*(volatile u32 __force *)addr)
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: "memory");
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}
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#define writeb __raw_writeb
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#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
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#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
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static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stb.ab r8, [r1, 1]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"stw.ab r8, [r1, 2]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.di r8, [r0]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab r8, [r1, 4]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
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{
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__asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (bytelen)
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: "r8");
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return bytelen;
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}
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static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
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{
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__asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (wordlen)
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: "r8");
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return wordlen;
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}
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static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
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{
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__asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
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"sub.f r2, r2, 1\n"
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"bnz.d 1b\n"
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"st.ab.di r8, [r0, 0]\n"
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:
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: "r" (addr), "r" (data), "r" (longlen)
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: "r8");
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return longlen;
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}
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#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
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#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
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#define out_le32(a, v) out_arch(l, le32, a, v)
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#define out_le16(a, v) out_arch(w, le16, a, v)
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#define in_le32(a) in_arch(l, le32, a)
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#define in_le16(a) in_arch(w, le16, a)
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#define out_be32(a, v) out_arch(l, be32, a, v)
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#define out_be16(a, v) out_arch(w, be16, a, v)
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#define in_be32(a) in_arch(l, be32, a)
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#define in_be16(a) in_arch(w, be16, a)
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#define out_8(a, v) __raw_writeb(v, a)
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#define in_8(a) __raw_readb(a)
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/*
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* Clear and set bits in one shot. These macros can be used to clear and
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* set multiple bits in a register using a single call. These macros can
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* also be used to set a multiple-bit bit pattern using a mask, by
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* specifying the mask in the 'clear' parameter and the new bit pattern
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* in the 'set' parameter.
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*/
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#define clrbits(type, addr, clear) \
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out_##type((addr), in_##type(addr) & ~(clear))
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#define setbits(type, addr, set) \
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out_##type((addr), in_##type(addr) | (set))
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#define clrsetbits(type, addr, clear, set) \
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out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
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#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
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#define setbits_be32(addr, set) setbits(be32, addr, set)
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#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
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#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
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#define setbits_le32(addr, set) setbits(le32, addr, set)
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#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
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#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
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#define setbits_be16(addr, set) setbits(be16, addr, set)
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#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
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#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
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#define setbits_le16(addr, set) setbits(le16, addr, set)
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#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
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#define clrbits_8(addr, clear) clrbits(8, addr, clear)
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#define setbits_8(addr, set) setbits(8, addr, set)
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#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
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#endif /* __ASM_ARC_IO_H */
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