upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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606 lines
16 KiB
606 lines
16 KiB
#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra124";
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interrupt-parent = <&gic>;
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pcie-controller@01003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x01003000 0x00000800 /* PADS registers */
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0x01003800 0x00000800 /* AFI registers */
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0x02000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
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0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
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0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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<&tegra_car TEGRA124_CLK_AFI>,
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<&tegra_car TEGRA124_CLK_PLL_E>,
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<&tegra_car TEGRA124_CLK_CML0>;
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clock-names = "pex", "afi", "pll_e", "cml";
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resets = <&tegra_car 70>,
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<&tegra_car 72>,
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<&tegra_car 74>;
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reset-names = "pex", "afi", "pcie_x";
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status = "disabled";
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phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
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phy-names = "pcie";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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host1x@50000000 {
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compatible = "nvidia,tegra124-host1x", "simple-bus";
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reg = <0x50000000 0x00034000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
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resets = <&tegra_car 28>;
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reset-names = "host1x";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x01000000>;
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dc@54200000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP1>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 27>;
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reset-names = "dc";
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nvidia,head = <0>;
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};
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dc@54240000 {
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compatible = "nvidia,tegra124-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DISP2>,
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<&tegra_car TEGRA124_CLK_PLL_P>;
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clock-names = "dc", "parent";
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resets = <&tegra_car 26>;
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reset-names = "dc";
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nvidia,head = <1>;
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};
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hdmi@54280000 {
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compatible = "nvidia,tegra124-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_HDMI>,
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<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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status = "disabled";
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};
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sor@54540000 {
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compatible = "nvidia,tegra124-sor";
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reg = <0x54540000 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SOR0>,
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<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
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<&tegra_car TEGRA124_CLK_PLL_DP>,
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<&tegra_car TEGRA124_CLK_CLK_M>;
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clock-names = "sor", "parent", "dp", "safe";
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resets = <&tegra_car 182>;
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reset-names = "sor";
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status = "disabled";
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};
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dpaux: dpaux@545c0000 {
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compatible = "nvidia,tegra124-dpaux";
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reg = <0x545c0000 0x00040000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
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<&tegra_car TEGRA124_CLK_PLL_DP>;
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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status = "disabled";
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};
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};
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x2000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma@60020000 {
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compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x60020000 0x1400>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 12>;
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <0 84 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 54>;
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <0 92 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 67>;
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <0 120 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 103>;
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <0 53 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 47>;
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status = "disabled";
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};
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i2c@7000d100 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000d100 0x100>;
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interrupts = <0 53 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 47>;
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status = "disabled";
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};
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uarta: serial@70006000 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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dmas = <&apbdma 19>, <&apbdma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uarte: serial@70006400 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTE>;
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resets = <&tegra_car 66>;
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reset-names = "serial";
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dmas = <&apbdma 20>, <&apbdma 20>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA124_CLK_PWM>;
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000d400 0x200>;
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interrupts = <0 59 0x04>;
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nvidia,dma-request-selector = <&apbdma 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 41>;
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};
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spi@7000d600 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000d600 0x200>;
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interrupts = <0 82 0x04>;
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nvidia,dma-request-selector = <&apbdma 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 44>;
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};
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spi@7000d800 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000d800 0x200>;
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interrupts = <0 83 0x04>;
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nvidia,dma-request-selector = <&apbdma 17>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 46>;
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};
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spi@7000da00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000da00 0x200>;
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interrupts = <0 93 0x04>;
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nvidia,dma-request-selector = <&apbdma 18>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 68>;
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};
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spi@7000dc00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000dc00 0x200>;
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interrupts = <0 94 0x04>;
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nvidia,dma-request-selector = <&apbdma 27>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 104>;
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};
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spi@7000de00 {
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compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
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reg = <0x7000de00 0x200>;
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interrupts = <0 79 0x04>;
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nvidia,dma-request-selector = <&apbdma 28>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&tegra_car 105>;
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};
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pmc@7000e400 {
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compatible = "nvidia,tegra124-pmc";
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reg = <0x7000e400 0x400>;
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};
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padctl: padctl@7009f000 {
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compatible = "nvidia,tegra124-xusb-padctl";
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reg = <0x7009f000 0x1000>;
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resets = <&tegra_car 142>;
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reset-names = "padctl";
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#phy-cells = <1>;
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};
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sdhci@700b0000 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0000 0x200>;
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interrupts = <0 14 0x04>;
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clocks = <&tegra_car 14>;
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status = "disabled";
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};
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sdhci@700b0200 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0200 0x200>;
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interrupts = <0 15 0x04>;
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clocks = <&tegra_car 9>;
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status = "disabled";
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};
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sdhci@700b0400 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0400 0x200>;
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interrupts = <0 19 0x04>;
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clocks = <&tegra_car 69>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@700b0600 {
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
reg = <0x700b0600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&tegra_car 15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ahub@70300000 {
|
|
compatible = "nvidia,tegra124-ahub";
|
|
reg = <0x70300000 0x200>,
|
|
<0x70300800 0x800>,
|
|
<0x70300200 0x600>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
|
|
<&tegra_car TEGRA124_CLK_APBIF>;
|
|
clock-names = "d_audio", "apbif";
|
|
resets = <&tegra_car 106>, /* d_audio */
|
|
<&tegra_car 107>, /* apbif */
|
|
<&tegra_car 30>, /* i2s0 */
|
|
<&tegra_car 11>, /* i2s1 */
|
|
<&tegra_car 18>, /* i2s2 */
|
|
<&tegra_car 101>, /* i2s3 */
|
|
<&tegra_car 102>, /* i2s4 */
|
|
<&tegra_car 108>, /* dam0 */
|
|
<&tegra_car 109>, /* dam1 */
|
|
<&tegra_car 110>, /* dam2 */
|
|
<&tegra_car 10>, /* spdif */
|
|
<&tegra_car 153>, /* amx */
|
|
<&tegra_car 185>, /* amx1 */
|
|
<&tegra_car 154>, /* adx */
|
|
<&tegra_car 180>, /* adx1 */
|
|
<&tegra_car 186>, /* afc0 */
|
|
<&tegra_car 187>, /* afc1 */
|
|
<&tegra_car 188>, /* afc2 */
|
|
<&tegra_car 189>, /* afc3 */
|
|
<&tegra_car 190>, /* afc4 */
|
|
<&tegra_car 191>; /* afc5 */
|
|
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
|
"spdif", "amx", "amx1", "adx", "adx1",
|
|
"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
|
|
dmas = <&apbdma 1>, <&apbdma 1>,
|
|
<&apbdma 2>, <&apbdma 2>,
|
|
<&apbdma 3>, <&apbdma 3>,
|
|
<&apbdma 4>, <&apbdma 4>,
|
|
<&apbdma 6>, <&apbdma 6>,
|
|
<&apbdma 7>, <&apbdma 7>,
|
|
<&apbdma 12>, <&apbdma 12>,
|
|
<&apbdma 13>, <&apbdma 13>,
|
|
<&apbdma 14>, <&apbdma 14>,
|
|
<&apbdma 29>, <&apbdma 29>;
|
|
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
|
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
|
|
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
|
|
"rx9", "tx9";
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
tegra_i2s0: i2s@70301000 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x70301000 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
|
|
resets = <&tegra_car 30>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70301100 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x70301100 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
|
|
resets = <&tegra_car 11>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70301200 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x70301200 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
|
|
resets = <&tegra_car 18>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70301300 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x70301300 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
|
|
resets = <&tegra_car 101>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70301400 {
|
|
compatible = "nvidia,tegra124-i2s";
|
|
reg = <0x70301400 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
|
|
resets = <&tegra_car 102>;
|
|
reset-names = "i2s";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
reg = <0x7d000000 0x4000>;
|
|
interrupts = < 52 >;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d004000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
reg = <0x7d004000 0x4000>;
|
|
interrupts = < 53 >;
|
|
phy_type = "hsic";
|
|
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@7d008000 {
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
reg = <0x7d008000 0x4000>;
|
|
interrupts = < 129 >;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|