upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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140 lines
3.0 KiB
140 lines
3.0 KiB
/*
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* (C) Copyright 2011
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* Julius Baxter, julius@opencores.org
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*
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* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <console.h>
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#include <stdio_dev.h>
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#include <watchdog.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <net.h>
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#ifdef CONFIG_STATUS_LED
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#include <status_led.h>
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#endif
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#ifdef CONFIG_CMD_NAND
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#include <nand.h> /* cannot even include nand.h if it isnt configured */
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#endif
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#include <timestamp.h>
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#include <version.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* All attempts to come up with a "common" initialization sequence
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* that works for all boards and architectures failed: some of the
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* requirements are just _too_ different. To get rid of the resulting
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* mess of board dependend #ifdef'ed code we now make the whole
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* initialization sequence configurable to the user.
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*
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* The requirements for any new initalization function is simple: it
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* receives a pointer to the "global data" structure as it's only
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* argument, and returns an integer return code, where 0 means
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* "continue" and != 0 means "fatal error, hang the system".
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*/
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extern int cache_init(void);
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/*
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* Initialization sequence
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*/
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static int (* const init_sequence[])(void) = {
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cache_init,
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timer_init, /* initialize timer */
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env_init,
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serial_init,
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console_init_f,
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display_options,
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checkcpu,
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checkboard,
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};
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/***********************************************************************/
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void board_init(void)
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{
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bd_t *bd;
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int i;
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gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
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memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
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gd->bd = (bd_t *)(gd+1); /* At end of global data */
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gd->baudrate = CONFIG_BAUDRATE;
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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bd = gd->bd;
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bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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#ifndef CONFIG_SYS_NO_FLASH
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bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
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#endif
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#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
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bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
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bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
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#endif
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for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
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WATCHDOG_RESET();
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if (init_sequence[i]())
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hang();
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}
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WATCHDOG_RESET();
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/* The Malloc area is immediately below the monitor copy in RAM */
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mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
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#ifndef CONFIG_SYS_NO_FLASH
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WATCHDOG_RESET();
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bd->bi_flashsize = flash_init();
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#endif
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#ifdef CONFIG_CMD_NAND
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puts("NAND: ");
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nand_init();
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#endif
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#ifdef CONFIG_GENERIC_MMC
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puts("MMC: ");
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mmc_initialize(bd);
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#endif
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WATCHDOG_RESET();
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env_relocate();
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WATCHDOG_RESET();
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stdio_init();
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jumptable_init();
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console_init_r();
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WATCHDOG_RESET();
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interrupt_init();
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#if defined(CONFIG_BOARD_LATE_INIT)
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board_late_init();
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#endif
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#if defined(CONFIG_CMD_NET)
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puts("NET: ");
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eth_initialize();
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#endif
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/* main_loop */
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for (;;) {
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WATCHDOG_RESET();
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main_loop();
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}
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}
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