upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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371 lines
11 KiB
371 lines
11 KiB
/*
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* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/omap_gpmc.h>
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#include <linux/mtd/nand_ecc.h>
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#include <nand.h>
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static uint8_t cs;
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static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
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/*
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* omap_nand_hwcontrol - Set the address pointers corretly for the
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* following address/data/command operation
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*/
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static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
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uint32_t ctrl)
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{
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register struct nand_chip *this = mtd->priv;
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/*
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* Point the IO_ADDR to DATA and ADDRESS registers instead
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* of chip address
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*/
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switch (ctrl) {
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case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
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break;
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case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
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break;
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case NAND_CTRL_CHANGE | NAND_NCE:
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this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
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break;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SPL_BUILD
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/* Check wait pin as dev ready indicator */
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int omap_spl_dev_ready(struct mtd_info *mtd)
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{
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return gpmc_cfg->status & (1 << 8);
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}
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#endif
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/*
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* omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
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* GPMC controller
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* @mtd: MTD device structure
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*
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*/
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static void omap_hwecc_init(struct nand_chip *chip)
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{
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/*
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* Init ECC Control Register
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* Clear all ECC | Enable Reg1
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*/
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
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}
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/*
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* gen_true_ecc - This function will generate true ECC value, which
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* can be used when correcting data read from NAND flash memory core
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*
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* @ecc_buf: buffer to store ecc code
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*
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* @return: re-formatted ECC value
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*/
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static uint32_t gen_true_ecc(uint8_t *ecc_buf)
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{
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return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
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((ecc_buf[2] & 0x0F) << 8);
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}
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/*
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* omap_correct_data - Compares the ecc read from nand spare area with ECC
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* registers values and corrects one bit error if it has occured
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* Further details can be had from OMAP TRM and the following selected links:
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* http://en.wikipedia.org/wiki/Hamming_code
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* http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
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*
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* @mtd: MTD device structure
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* @dat: page data
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* @read_ecc: ecc read from nand flash
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* @calc_ecc: ecc read from ECC registers
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*
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* @return 0 if data is OK or corrected, else returns -1
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*/
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static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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uint32_t orig_ecc, new_ecc, res, hm;
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uint16_t parity_bits, byte;
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uint8_t bit;
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/* Regenerate the orginal ECC */
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orig_ecc = gen_true_ecc(read_ecc);
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new_ecc = gen_true_ecc(calc_ecc);
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/* Get the XOR of real ecc */
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res = orig_ecc ^ new_ecc;
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if (res) {
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/* Get the hamming width */
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hm = hweight32(res);
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/* Single bit errors can be corrected! */
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if (hm == 12) {
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/* Correctable data! */
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parity_bits = res >> 16;
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bit = (parity_bits & 0x7);
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byte = (parity_bits >> 3) & 0x1FF;
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/* Flip the bit to correct */
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dat[byte] ^= (0x1 << bit);
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} else if (hm == 1) {
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printf("Error: Ecc is wrong\n");
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/* ECC itself is corrupted */
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return 2;
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} else {
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/*
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* hm distance != parity pairs OR one, could mean 2 bit
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* error OR potentially be on a blank page..
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* orig_ecc: contains spare area data from nand flash.
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* new_ecc: generated ecc while reading data area.
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* Note: if the ecc = 0, all data bits from which it was
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* generated are 0xFF.
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* The 3 byte(24 bits) ecc is generated per 512byte
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* chunk of a page. If orig_ecc(from spare area)
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* is 0xFF && new_ecc(computed now from data area)=0x0,
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* this means that data area is 0xFF and spare area is
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* 0xFF. A sure sign of a erased page!
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*/
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if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
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return 0;
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printf("Error: Bad compare! failed\n");
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/* detected 2 bit error */
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return -1;
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}
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}
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return 0;
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}
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/*
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* omap_calculate_ecc - Generate non-inverted ECC bytes.
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*
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* Using noninverted ECC can be considered ugly since writing a blank
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* page ie. padding will clear the ECC bytes. This is no problem as
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* long nobody is trying to write data on the seemingly unused page.
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* Reading an erased page will produce an ECC mismatch between
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* generated and read ECC bytes that has to be dealt with separately.
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* E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
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* is used, the result of read will be 0x0 while the ECC offsets of the
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* spare area will be 0xFF which will result in an ECC mismatch.
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* @mtd: MTD structure
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* @dat: unused
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* @ecc_code: ecc_code buffer
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*/
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static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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u_int32_t val;
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/* Start Reading from HW ECC1_Result = 0x200 */
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val = readl(&gpmc_cfg->ecc1_result);
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ecc_code[0] = val & 0xFF;
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ecc_code[1] = (val >> 16) & 0xFF;
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ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
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/*
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* Stop reading anymore ECC vals and clear old results
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* enable will be called if more reads are required
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*/
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writel(0x000, &gpmc_cfg->ecc_config);
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return 0;
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}
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/*
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* omap_enable_ecc - This function enables the hardware ecc functionality
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* @mtd: MTD device structure
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* @mode: Read/Write mode
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*/
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static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
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switch (mode) {
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case NAND_ECC_READ:
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case NAND_ECC_WRITE:
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/* Clear the ecc result registers, select ecc reg as 1 */
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
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/*
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* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
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* tell all regs to generate size0 sized regs
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* we just have a single ECC engine for all CS
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*/
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writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
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&gpmc_cfg->ecc_size_config);
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val = (dev_width << 7) | (cs << 1) | (0x1);
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writel(val, &gpmc_cfg->ecc_config);
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break;
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default:
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printf("Error: Unrecognized Mode[%d]!\n", mode);
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break;
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}
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}
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#ifndef CONFIG_SPL_BUILD
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/*
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* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
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* The default is to come up on s/w ecc
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*
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* @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
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*
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*/
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void omap_nand_switch_ecc(int32_t hardware)
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{
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struct nand_chip *nand;
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struct mtd_info *mtd;
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if (nand_curr_device < 0 ||
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nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
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!nand_info[nand_curr_device].name) {
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printf("Error: Can't switch ecc, no devices available\n");
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return;
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}
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mtd = &nand_info[nand_curr_device];
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nand = mtd->priv;
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nand->options |= NAND_OWN_BUFFERS;
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/* Reset ecc interface */
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nand->ecc.read_page = NULL;
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nand->ecc.write_page = NULL;
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nand->ecc.read_oob = NULL;
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nand->ecc.write_oob = NULL;
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nand->ecc.hwctl = NULL;
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nand->ecc.correct = NULL;
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nand->ecc.calculate = NULL;
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/* Setup the ecc configurations again */
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if (hardware) {
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_nand_oob;
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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nand->ecc.hwctl = omap_enable_hwecc;
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nand->ecc.correct = omap_correct_data;
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nand->ecc.calculate = omap_calculate_ecc;
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omap_hwecc_init(nand);
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printf("HW ECC selected\n");
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} else {
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Use mtd default settings */
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nand->ecc.layout = NULL;
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printf("SW ECC selected\n");
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}
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/* Update NAND handling after ECC mode switch */
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nand_scan_tail(mtd);
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nand->options &= ~NAND_OWN_BUFFERS;
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}
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific:
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* - IO_ADDR_R: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W: address to write the 8 I/O lines of the flash device
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* - cmd_ctrl: hardwarespecific function for accesing control-lines
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* - waitfunc: hardwarespecific function for accesing device ready/busy line
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* - ecc.hwctl: function to enable (reset) hardware ecc generator
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* - ecc.mode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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*/
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int board_nand_init(struct nand_chip *nand)
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{
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int32_t gpmc_config = 0;
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cs = 0;
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/*
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* xloader/Uboot's gpmc configuration would have configured GPMC for
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* nand type of memory. The following logic scans and latches on to the
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* first CS with NAND type memory.
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* TBD: need to make this logic generic to handle multiple CS NAND
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* devices.
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*/
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while (cs < GPMC_MAX_CS) {
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/* Check if NAND type is set */
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if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
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/* Found it!! */
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break;
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}
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cs++;
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}
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if (cs >= GPMC_MAX_CS) {
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printf("NAND: Unable to find NAND settings in "
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"GPMC Configuration - quitting\n");
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return -ENODEV;
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}
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gpmc_config = readl(&gpmc_cfg->config);
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/* Disable Write protect */
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gpmc_config |= 0x10;
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writel(gpmc_config, &gpmc_cfg->config);
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nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
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nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
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nand->cmd_ctrl = omap_nand_hwcontrol;
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nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
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/* If we are 16 bit dev, our gpmc config tells us that */
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if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
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nand->options |= NAND_BUSWIDTH_16;
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nand->chip_delay = 100;
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/* Default ECC mode */
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#ifndef CONFIG_SPL_BUILD
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nand->ecc.mode = NAND_ECC_SOFT;
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#else
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_nand_oob;
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nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
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nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
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nand->ecc.hwctl = omap_enable_hwecc;
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nand->ecc.correct = omap_correct_data;
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nand->ecc.calculate = omap_calculate_ecc;
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omap_hwecc_init(nand);
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if (nand->options & NAND_BUSWIDTH_16)
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nand->read_buf = nand_read_buf16;
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else
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nand->read_buf = nand_read_buf;
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nand->dev_ready = omap_spl_dev_ready;
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#endif
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return 0;
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}
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