upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
2.3 KiB
77 lines
2.3 KiB
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <asm/arch/tegra2.h>
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#include "serial_tegra2.h"
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static void setup_uart(struct uart_ctlr *u)
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{
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u32 reg;
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/* Prepare the divisor value */
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reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
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/* Set up UART parameters */
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writel(UART_LCR_DLAB, &u->uart_lcr);
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writel(reg, &u->uart_thr_dlab_0);
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writel(0, &u->uart_ier_dlab_0);
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writel(0, &u->uart_lcr); /* clear DLAB */
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writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
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UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
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writel(0, &u->uart_ier_dlab_0);
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writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */
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writel(UART_MCR_RTS, &u->uart_mcr);
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writel(0, &u->uart_msr);
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writel(0, &u->uart_spr);
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writel(0, &u->uart_irda_csr);
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writel(0, &u->uart_asr);
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writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
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/* Flush any old characters out of the RX FIFO */
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reg = readl(&u->uart_lsr);
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while (reg & UART_LSR_DR) {
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reg = readl(&u->uart_thr_dlab_0);
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reg = readl(&u->uart_lsr);
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}
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}
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/*
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* Routine: uart_init
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* Description: init the UART clocks, muxes, and baudrate/parity/etc.
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*/
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void uart_init(void)
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{
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struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE;
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#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
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setup_uart(uart);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
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uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE;
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setup_uart(uart);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
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}
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