upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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555 lines
13 KiB
555 lines
13 KiB
/*
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* (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
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*
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* This driver for AMD PCnet network controllers is derived from the
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* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <pci.h>
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#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
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#define PCNET_DEBUG1(fmt,args...) \
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debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
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#define PCNET_DEBUG2(fmt,args...) \
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debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
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#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
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#error "Macro for PCnet chip version is not defined!"
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#endif
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/*
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* Set the number of Tx and Rx buffers, using Log_2(# buffers).
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* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
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* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
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*/
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#define PCNET_LOG_TX_BUFFERS 0
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#define PCNET_LOG_RX_BUFFERS 2
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#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
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#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
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#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
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#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
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#define PKT_BUF_SZ 1544
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/* The PCNET Rx and Tx ring descriptors. */
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struct pcnet_rx_head {
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u32 base;
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s16 buf_length;
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s16 status;
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u32 msg_length;
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u32 reserved;
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};
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struct pcnet_tx_head {
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u32 base;
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s16 length;
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s16 status;
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u32 misc;
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u32 reserved;
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};
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/* The PCNET 32-Bit initialization block, described in databook. */
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struct pcnet_init_block {
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u16 mode;
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u16 tlen_rlen;
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u8 phys_addr[6];
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u16 reserved;
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u32 filter[2];
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/* Receive and transmit ring base, along with extra bits. */
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u32 rx_ring;
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u32 tx_ring;
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u32 reserved2;
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};
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struct pcnet_uncached_priv {
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struct pcnet_rx_head rx_ring[RX_RING_SIZE];
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struct pcnet_tx_head tx_ring[TX_RING_SIZE];
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struct pcnet_init_block init_block;
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};
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typedef struct pcnet_priv {
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struct pcnet_uncached_priv *uc;
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/* Receive Buffer space */
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unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
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int cur_rx;
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int cur_tx;
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} pcnet_priv_t;
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static pcnet_priv_t *lp;
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/* Offsets from base I/O address for WIO mode */
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#define PCNET_RDP 0x10
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#define PCNET_RAP 0x12
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#define PCNET_RESET 0x14
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#define PCNET_BDP 0x16
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static u16 pcnet_read_csr(struct eth_device *dev, int index)
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{
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outw(index, dev->iobase + PCNET_RAP);
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return inw(dev->iobase + PCNET_RDP);
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}
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static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
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{
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outw(index, dev->iobase + PCNET_RAP);
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outw(val, dev->iobase + PCNET_RDP);
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}
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static u16 pcnet_read_bcr(struct eth_device *dev, int index)
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{
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outw(index, dev->iobase + PCNET_RAP);
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return inw(dev->iobase + PCNET_BDP);
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}
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static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
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{
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outw(index, dev->iobase + PCNET_RAP);
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outw(val, dev->iobase + PCNET_BDP);
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}
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static void pcnet_reset(struct eth_device *dev)
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{
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inw(dev->iobase + PCNET_RESET);
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}
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static int pcnet_check(struct eth_device *dev)
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{
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outw(88, dev->iobase + PCNET_RAP);
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return inw(dev->iobase + PCNET_RAP) == 88;
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}
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static int pcnet_init (struct eth_device *dev, bd_t * bis);
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static int pcnet_send(struct eth_device *dev, void *packet, int length);
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static int pcnet_recv (struct eth_device *dev);
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static void pcnet_halt (struct eth_device *dev);
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static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
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static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
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void *addr)
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{
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pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
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void *virt_addr = addr;
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return pci_virt_to_mem(devbusfn, virt_addr);
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}
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
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{}
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};
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int pcnet_initialize(bd_t *bis)
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{
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pci_dev_t devbusfn;
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struct eth_device *dev;
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u16 command, status;
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int dev_nr = 0;
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u32 bar;
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PCNET_DEBUG1("\npcnet_initialize...\n");
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for (dev_nr = 0;; dev_nr++) {
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/*
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* Find the PCnet PCI device(s).
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*/
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devbusfn = pci_find_devices(supported, dev_nr);
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if (devbusfn < 0)
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break;
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/*
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* Allocate and pre-fill the device structure.
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*/
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dev = (struct eth_device *)malloc(sizeof(*dev));
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if (!dev) {
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printf("pcnet: Can not allocate memory\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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dev->priv = (void *)(unsigned long)devbusfn;
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sprintf(dev->name, "pcnet#%d", dev_nr);
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/*
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* Setup the PCI device.
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*/
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
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dev->iobase = pci_io_to_phys(devbusfn, bar);
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dev->iobase &= ~0xf;
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PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
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dev->name, devbusfn, (unsigned long)dev->iobase);
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command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
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pci_write_config_word(devbusfn, PCI_COMMAND, command);
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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if ((status & command) != command) {
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printf("%s: Couldn't enable IO access or Bus Mastering\n",
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dev->name);
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free(dev);
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continue;
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}
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pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
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/*
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* Probe the PCnet chip.
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*/
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if (pcnet_probe(dev, bis, dev_nr) < 0) {
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free(dev);
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continue;
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}
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/*
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* Setup device structure and register the driver.
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*/
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dev->init = pcnet_init;
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dev->halt = pcnet_halt;
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dev->send = pcnet_send;
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dev->recv = pcnet_recv;
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eth_register(dev);
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}
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udelay(10 * 1000);
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return dev_nr;
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}
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static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
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{
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int chip_version;
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char *chipname;
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#ifdef PCNET_HAS_PROM
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int i;
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#endif
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/* Reset the PCnet controller */
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pcnet_reset(dev);
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/* Check if register access is working */
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if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
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printf("%s: CSR register access check failed\n", dev->name);
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return -1;
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}
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/* Identify the chip */
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chip_version =
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pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
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if ((chip_version & 0xfff) != 0x003)
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return -1;
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chip_version = (chip_version >> 12) & 0xffff;
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switch (chip_version) {
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case 0x2621:
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chipname = "PCnet/PCI II 79C970A"; /* PCI */
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break;
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#ifdef CONFIG_PCNET_79C973
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case 0x2625:
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chipname = "PCnet/FAST III 79C973"; /* PCI */
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break;
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#endif
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#ifdef CONFIG_PCNET_79C975
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case 0x2627:
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chipname = "PCnet/FAST III 79C975"; /* PCI */
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break;
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#endif
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default:
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printf("%s: PCnet version %#x not supported\n",
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dev->name, chip_version);
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return -1;
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}
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PCNET_DEBUG1("AMD %s\n", chipname);
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#ifdef PCNET_HAS_PROM
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/*
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* In most chips, after a chip reset, the ethernet address is read from
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* the station address PROM at the base address and programmed into the
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* "Physical Address Registers" CSR12-14.
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*/
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for (i = 0; i < 3; i++) {
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unsigned int val;
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val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
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/* There may be endianness issues here. */
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dev->enetaddr[2 * i] = val & 0x0ff;
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dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
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}
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#endif /* PCNET_HAS_PROM */
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return 0;
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}
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static int pcnet_init(struct eth_device *dev, bd_t *bis)
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{
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struct pcnet_uncached_priv *uc;
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int i, val;
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unsigned long addr;
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PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
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/* Switch pcnet to 32bit mode */
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pcnet_write_bcr(dev, 20, 2);
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/* Set/reset autoselect bit */
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val = pcnet_read_bcr(dev, 2) & ~2;
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val |= 2;
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pcnet_write_bcr(dev, 2, val);
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/* Enable auto negotiate, setup, disable fd */
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val = pcnet_read_bcr(dev, 32) & ~0x98;
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val |= 0x20;
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pcnet_write_bcr(dev, 32, val);
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/*
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* Enable NOUFLO on supported controllers, with the transmit
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* start point set to the full packet. This will cause entire
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* packets to be buffered by the ethernet controller before
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* transmission, eliminating underflows which are common on
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* slower devices. Controllers which do not support NOUFLO will
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* simply be left with a larger transmit FIFO threshold.
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*/
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val = pcnet_read_bcr(dev, 18);
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val |= 1 << 11;
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pcnet_write_bcr(dev, 18, val);
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val = pcnet_read_csr(dev, 80);
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val |= 0x3 << 10;
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pcnet_write_csr(dev, 80, val);
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/*
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* We only maintain one structure because the drivers will never
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* be used concurrently. In 32bit mode the RX and TX ring entries
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* must be aligned on 16-byte boundaries.
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*/
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if (lp == NULL) {
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addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
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addr = (addr + 0xf) & ~0xf;
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lp = (pcnet_priv_t *)addr;
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addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
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sizeof(*lp->uc));
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flush_dcache_range(addr, addr + sizeof(*lp->uc));
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addr = UNCACHED_SDRAM(addr);
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lp->uc = (struct pcnet_uncached_priv *)addr;
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addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
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sizeof(*lp->rx_buf));
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flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
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lp->rx_buf = (void *)addr;
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}
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uc = lp->uc;
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uc->init_block.mode = cpu_to_le16(0x0000);
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uc->init_block.filter[0] = 0x00000000;
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uc->init_block.filter[1] = 0x00000000;
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/*
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* Initialize the Rx ring.
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*/
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lp->cur_rx = 0;
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for (i = 0; i < RX_RING_SIZE; i++) {
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addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
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uc->rx_ring[i].base = cpu_to_le32(addr);
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uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
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uc->rx_ring[i].status = cpu_to_le16(0x8000);
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PCNET_DEBUG1
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("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
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uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
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uc->rx_ring[i].status);
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}
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/*
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* Initialize the Tx ring. The Tx buffer address is filled in as
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* needed, but we do need to clear the upper ownership bit.
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*/
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lp->cur_tx = 0;
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for (i = 0; i < TX_RING_SIZE; i++) {
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uc->tx_ring[i].base = 0;
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uc->tx_ring[i].status = 0;
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}
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/*
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* Setup Init Block.
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*/
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PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
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for (i = 0; i < 6; i++) {
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lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
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PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
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}
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uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
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RX_RING_LEN_BITS);
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addr = pcnet_virt_to_mem(dev, uc->rx_ring);
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uc->init_block.rx_ring = cpu_to_le32(addr);
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addr = pcnet_virt_to_mem(dev, uc->tx_ring);
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uc->init_block.tx_ring = cpu_to_le32(addr);
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PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
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uc->init_block.tlen_rlen,
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uc->init_block.rx_ring, uc->init_block.tx_ring);
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/*
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* Tell the controller where the Init Block is located.
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*/
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barrier();
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addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
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pcnet_write_csr(dev, 1, addr & 0xffff);
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pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
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pcnet_write_csr(dev, 4, 0x0915);
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pcnet_write_csr(dev, 0, 0x0001); /* start */
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/* Wait for Init Done bit */
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for (i = 10000; i > 0; i--) {
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if (pcnet_read_csr(dev, 0) & 0x0100)
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break;
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udelay(10);
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: controller init failed\n", dev->name);
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pcnet_reset(dev);
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return -1;
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}
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/*
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* Finally start network controller operation.
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*/
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pcnet_write_csr(dev, 0, 0x0002);
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return 0;
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}
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static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
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{
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int i, status;
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u32 addr;
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struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
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PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
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packet);
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flush_dcache_range((unsigned long)packet,
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(unsigned long)packet + pkt_len);
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/* Wait for completion by testing the OWN bit */
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for (i = 1000; i > 0; i--) {
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status = readw(&entry->status);
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if ((status & 0x8000) == 0)
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break;
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udelay(100);
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PCNET_DEBUG2(".");
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}
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if (i <= 0) {
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printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
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dev->name, lp->cur_tx, status);
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pkt_len = 0;
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goto failure;
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}
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/*
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* Setup Tx ring. Caution: the write order is important here,
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* set the status with the "ownership" bits last.
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*/
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addr = pcnet_virt_to_mem(dev, packet);
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writew(-pkt_len, &entry->length);
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writel(0, &entry->misc);
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writel(addr, &entry->base);
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writew(0x8300, &entry->status);
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/* Trigger an immediate send poll. */
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pcnet_write_csr(dev, 0, 0x0008);
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failure:
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if (++lp->cur_tx >= TX_RING_SIZE)
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lp->cur_tx = 0;
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PCNET_DEBUG2("done\n");
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return pkt_len;
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}
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static int pcnet_recv (struct eth_device *dev)
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{
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struct pcnet_rx_head *entry;
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unsigned char *buf;
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int pkt_len = 0;
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u16 status, err_status;
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while (1) {
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entry = &lp->uc->rx_ring[lp->cur_rx];
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/*
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* If we own the next entry, it's a new packet. Send it up.
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*/
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status = readw(&entry->status);
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if ((status & 0x8000) != 0)
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break;
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err_status = status >> 8;
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if (err_status != 0x03) { /* There was an error. */
|
|
printf("%s: Rx%d", dev->name, lp->cur_rx);
|
|
PCNET_DEBUG1(" (status=0x%x)", err_status);
|
|
if (err_status & 0x20)
|
|
printf(" Frame");
|
|
if (err_status & 0x10)
|
|
printf(" Overflow");
|
|
if (err_status & 0x08)
|
|
printf(" CRC");
|
|
if (err_status & 0x04)
|
|
printf(" Fifo");
|
|
printf(" Error\n");
|
|
status &= 0x03ff;
|
|
|
|
} else {
|
|
pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
|
|
if (pkt_len < 60) {
|
|
printf("%s: Rx%d: invalid packet length %d\n",
|
|
dev->name, lp->cur_rx, pkt_len);
|
|
} else {
|
|
buf = (*lp->rx_buf)[lp->cur_rx];
|
|
invalidate_dcache_range((unsigned long)buf,
|
|
(unsigned long)buf + pkt_len);
|
|
net_process_received_packet(buf, pkt_len);
|
|
PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
|
|
lp->cur_rx, pkt_len, buf);
|
|
}
|
|
}
|
|
|
|
status |= 0x8000;
|
|
writew(status, &entry->status);
|
|
|
|
if (++lp->cur_rx >= RX_RING_SIZE)
|
|
lp->cur_rx = 0;
|
|
}
|
|
return pkt_len;
|
|
}
|
|
|
|
static void pcnet_halt(struct eth_device *dev)
|
|
{
|
|
int i;
|
|
|
|
PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
|
|
|
|
/* Reset the PCnet controller */
|
|
pcnet_reset(dev);
|
|
|
|
/* Wait for Stop bit */
|
|
for (i = 1000; i > 0; i--) {
|
|
if (pcnet_read_csr(dev, 0) & 0x4)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
if (i <= 0)
|
|
printf("%s: TIMEOUT: controller reset failed\n", dev->name);
|
|
}
|
|
|