upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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88 lines
2.6 KiB
88 lines
2.6 KiB
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EMIF_DEFS_H_
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#define _EMIF_DEFS_H_
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#include <asm/arch/hardware.h>
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struct davinci_emif_regs {
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u_int32_t ercsr;
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u_int32_t awccr;
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u_int32_t sdbcr;
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u_int32_t sdrcr;
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u_int32_t ab1cr;
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u_int32_t ab2cr;
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u_int32_t ab3cr;
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u_int32_t ab4cr;
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u_int32_t sdtimr;
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u_int32_t ddrsr;
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u_int32_t ddrphycr;
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u_int32_t ddrphysr;
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u_int32_t totar;
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u_int32_t totactr;
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u_int32_t ddrphyid_rev;
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u_int32_t sdsretr;
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u_int32_t eirr;
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u_int32_t eimr;
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u_int32_t eimsr;
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u_int32_t eimcr;
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u_int32_t ioctrlr;
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u_int32_t iostatr;
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u_int8_t rsvd0[8];
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u_int32_t nandfcr;
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u_int32_t nandfsr;
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u_int8_t rsvd1[8];
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u_int32_t nandfecc[4];
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u_int8_t rsvd2[60];
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u_int32_t nand4biteccload;
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u_int32_t nand4bitecc[4];
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u_int32_t nanderradd1;
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u_int32_t nanderradd2;
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u_int32_t nanderrval1;
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u_int32_t nanderrval2;
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};
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#define davinci_emif_regs \
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((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
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#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
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#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
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#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
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#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
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#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
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/* Chip Select setup */
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#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
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#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
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#define DAVINCI_ABCR_WSETUP(n) (n << 26)
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#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
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#define DAVINCI_ABCR_WHOLD(n) (n << 17)
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#define DAVINCI_ABCR_RSETUP(n) (n << 13)
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#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
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#define DAVINCI_ABCR_RHOLD(n) (n << 4)
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#define DAVINCI_ABCR_TA(n) (n << 2)
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#define DAVINCI_ABCR_ASIZE_16BIT 1
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#define DAVINCI_ABCR_ASIZE_8BIT 0
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#endif
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