upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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441 lines
10 KiB
441 lines
10 KiB
/*
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* tsec.c
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* Motorola Three Speed Ethernet Controller driver
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* (C) Copyright 2003, Motorola, Inc.
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* maintained by Xianghua Xiao (x.xiao@motorola.com)
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* author Andy Fleming
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*
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*/
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#include <config.h>
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#include <mpc85xx.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#if defined(CONFIG_TSEC_ENET)
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#include "tsec.h"
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#define TX_BUF_CNT 2
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#undef TSEC_DEBUG
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#ifdef TSEC_DEBUG
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#define DBGPRINT(x) printf(x)
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#else
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#define DBGPRINT(x)
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#endif
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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typedef volatile struct rtxbd {
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txbd8_t txbd[TX_BUF_CNT];
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rxbd8_t rxbd[PKTBUFSRX];
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} RTXBD;
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#ifdef __GNUC__
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static RTXBD rtx __attribute__ ((aligned(8)));
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#else
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#error "rtx must be 64-bit aligned"
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#endif
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static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
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static int tsec_recv(struct eth_device* dev);
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static int tsec_init(struct eth_device* dev, bd_t * bd);
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static void tsec_halt(struct eth_device* dev);
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static void init_registers(tsec_t *regs);
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static void startup_tsec(tsec_t *regs);
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static void init_phy(tsec_t *regs);
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/* Initialize device structure. returns 0 on failure, 1 on
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* success */
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int tsec_initialize(bd_t *bis)
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{
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struct eth_device* dev;
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int i;
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dev = (struct eth_device*) malloc(sizeof *dev);
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if(dev == NULL)
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return 0;
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memset(dev, 0, sizeof *dev);
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sprintf(dev->name, "MOTOROLA ETHERNET");
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dev->iobase = 0;
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dev->priv = 0;
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dev->init = tsec_init;
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dev->halt = tsec_halt;
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dev->send = tsec_send;
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dev->recv = tsec_recv;
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/* Tell u-boot to get the addr from the env */
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for(i=0;i<6;i++)
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dev->enetaddr[i] = 0;
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eth_register(dev);
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return 1;
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}
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/* Initializes data structures and registers for the controller,
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* and brings the interface up */
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int tsec_init(struct eth_device* dev, bd_t * bd)
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{
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tsec_t *regs;
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uint tempval;
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char tmpbuf[MAC_ADDR_LEN];
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int i;
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regs = (tsec_t *)(TSEC_BASE_ADDR);
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/* Make sure the controller is stopped */
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tsec_halt(dev);
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/* Reset the MAC */
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regs->maccfg1 |= MACCFG1_SOFT_RESET;
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/* Clear MACCFG1[Soft_Reset] */
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regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
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/* Init MACCFG2. Defaults to GMII/MII */
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regs->maccfg2 = MACCFG2_INIT_SETTINGS;
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/* Init ECNTRL */
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regs->ecntrl = ECNTRL_INIT_SETTINGS;
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/* Copy the station address into the address registers.
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* Backwards, because little endian MACS are dumb */
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for(i=0;i<MAC_ADDR_LEN;i++) {
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tmpbuf[MAC_ADDR_LEN - 1 - i] = bd->bi_enetaddr[i];
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}
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(uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
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tempval = *((uint *)(tmpbuf +4));
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(uint)(regs->macstnaddr2) = tempval;
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/* Initialize the PHY */
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init_phy(regs);
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/* reset the indices to zero */
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rxIdx = 0;
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txIdx = 0;
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/* Clear out (for the most part) the other registers */
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init_registers(regs);
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/* Ready the device for tx/rx */
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startup_tsec(regs);
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return 1;
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}
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/* Reads from the register at offset in the PHY at phyid, */
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/* using the register set defined in regbase. It waits until the */
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/* bits in the miimstat are valid (miimind notvalid bit cleared), */
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/* and then passes those bits on to the variable specified in */
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/* value */
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/* Before it does the read, it needs to clear the command field */
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uint read_phy_reg(tsec_t *regbase, uint phyid, uint offset)
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{
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uint value;
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/* Put the address of the phy, and the register number into
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* MIIMADD
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*/
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regbase->miimadd = (phyid << 8) | offset;
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/* Clear the command register, and wait */
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regbase->miimcom = 0;
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asm("msync");
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/* Initiate a read command, and wait */
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regbase->miimcom = MIIM_READ_COMMAND;
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asm("msync");
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/* Wait for the the indication that the read is done */
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while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
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/* Grab the value read from the PHY */
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value = regbase->miimstat;
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return value;
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}
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/* Setup the PHY */
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static void init_phy(tsec_t *regs)
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{
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uint testval;
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unsigned int timeout = TSEC_TIMEOUT;
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/* Assign a Physical address to the TBI */
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regs->tbipa=TBIPA_VALUE;
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/* reset the management interface */
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regs->miimcfg=MIIMCFG_RESET;
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regs->miimcfg=MIIMCFG_INIT_VALUE;
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/* Wait until the bus is free */
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while(regs->miimind & MIIMIND_BUSY);
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#ifdef CONFIG_PHY_CIS8201
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/* override PHY config settings */
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write_phy_reg(regs, 0, MIIM_AUX_CONSTAT, MIIM_AUXCONSTAT_INIT);
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/* Set up interface mode */
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write_phy_reg(regs, 0, MIIM_EXT_CON1, MIIM_EXTCON1_INIT);
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#endif
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/* Set the PHY to gigabit, full duplex, Auto-negotiate */
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write_phy_reg(regs, 0, MIIM_CONTROL, MIIM_CONTROL_INIT);
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/* Wait until TBI_STATUS indicates AN is done */
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DBGPRINT("Waiting for Auto-negotiation to complete\n");
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testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
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while((!(testval & MIIM_TBI_STATUS_AN_DONE))&& timeout--) {
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testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
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}
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if(testval & MIIM_TBI_STATUS_AN_DONE)
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DBGPRINT("Auto-negotiation done\n");
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else
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DBGPRINT("Auto-negotiation timed-out.\n");
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#ifdef CONFIG_PHY_CIS8201
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/* Find out what duplexity (duplicity?) we have */
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/* Read it twice to make sure */
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testval=read_phy_reg(regs, 0, MIIM_AUX_CONSTAT);
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if(testval & MIIM_AUXCONSTAT_DUPLEX) {
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DBGPRINT("Enet starting in full duplex\n");
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regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
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} else {
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DBGPRINT("Enet starting in half duplex\n");
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regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
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}
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/* Also, we look to see what speed we are at
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* if Gigabit, MACCFG2 goes in GMII, otherwise,
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* MII mode.
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*/
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if((testval & MIIM_AUXCONSTAT_SPEED) != MIIM_AUXCONSTAT_GBIT) {
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if((testval & MIIM_AUXCONSTAT_SPEED) == MIIM_AUXCONSTAT_100)
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DBGPRINT("Enet starting in 100BT\n");
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else
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DBGPRINT("Enet starting in 10BT\n");
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/* mark the mode in MACCFG2 */
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regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
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} else {
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DBGPRINT("Enet starting in 1000BT\n");
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}
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#endif
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#ifdef CONFIG_PHY_M88E1011
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/* Read the PHY to see what speed and duplex we are */
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testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
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timeout = TSEC_TIMEOUT;
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while((!(testval & MIIM_PHYSTAT_SPDDONE)) && timeout--) {
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testval = read_phy_reg(regs,0,MIIM_PHY_STATUS);
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}
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if(!(testval & MIIM_PHYSTAT_SPDDONE))
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DBGPRINT("Enet: Speed not resolved\n");
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testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
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if(testval & MIIM_PHYSTAT_DUPLEX) {
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DBGPRINT("Enet starting in Full Duplex\n");
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regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
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} else {
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DBGPRINT("Enet starting in Half Duplex\n");
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regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
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}
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if(!((testval&MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_GBIT)) {
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if((testval & MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_100)
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DBGPRINT("Enet starting in 100BT\n");
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else
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DBGPRINT("Enet starting in 10BT\n");
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regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
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} else {
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DBGPRINT("Enet starting in 1000BT\n");
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}
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#endif
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}
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static void init_registers(tsec_t *regs)
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{
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/* Clear IEVENT */
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regs->ievent = IEVENT_INIT_CLEAR;
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regs->imask = IMASK_INIT_CLEAR;
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regs->hash.iaddr0 = 0;
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regs->hash.iaddr1 = 0;
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regs->hash.iaddr2 = 0;
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regs->hash.iaddr3 = 0;
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regs->hash.iaddr4 = 0;
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regs->hash.iaddr5 = 0;
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regs->hash.iaddr6 = 0;
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regs->hash.iaddr7 = 0;
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regs->hash.gaddr0 = 0;
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regs->hash.gaddr1 = 0;
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regs->hash.gaddr2 = 0;
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regs->hash.gaddr3 = 0;
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regs->hash.gaddr4 = 0;
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regs->hash.gaddr5 = 0;
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regs->hash.gaddr6 = 0;
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regs->hash.gaddr7 = 0;
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regs->rctrl = 0x00000000;
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/* Init RMON mib registers */
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memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
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regs->rmon.cam1 = 0xffffffff;
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regs->rmon.cam2 = 0xffffffff;
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regs->mrblr = MRBLR_INIT_SETTINGS;
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regs->minflr = MINFLR_INIT_SETTINGS;
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regs->attr = ATTR_INIT_SETTINGS;
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regs->attreli = ATTRELI_INIT_SETTINGS;
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}
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static void startup_tsec(tsec_t *regs)
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{
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int i;
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/* Point to the buffer descriptors */
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regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
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regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
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/* Initialize the Rx Buffer descriptors */
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for (i = 0; i < PKTBUFSRX; i++) {
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rtx.rxbd[i].status = RXBD_EMPTY;
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rtx.rxbd[i].length = 0;
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rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
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}
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rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
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/* Initialize the TX Buffer Descriptors */
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for(i=0; i<TX_BUF_CNT; i++) {
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rtx.txbd[i].status = 0;
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rtx.txbd[i].length = 0;
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rtx.txbd[i].bufPtr = 0;
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}
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rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
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/* Enable Transmit and Receive */
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regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
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/* Tell the DMA it is clear to go */
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regs->dmactrl |= DMACTRL_INIT_SETTINGS;
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regs->tstat = TSTAT_CLEAR_THALT;
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regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
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}
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/* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* errors */
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static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
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{
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int i;
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int result = 0;
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tsec_t * regs = (tsec_t *)(TSEC_BASE_ADDR);
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/* Find an empty buffer descriptor */
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for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
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if (i >= TOUT_LOOP) {
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DBGPRINT("tsec: tx buffers full\n");
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return result;
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}
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}
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rtx.txbd[txIdx].bufPtr = (uint)packet;
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rtx.txbd[txIdx].length = length;
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rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
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/* Tell the DMA to go */
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regs->tstat = TSTAT_CLEAR_THALT;
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/* Wait for buffer to be transmitted */
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for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
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if (i >= TOUT_LOOP) {
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DBGPRINT("tsec: tx error\n");
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return result;
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}
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}
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txIdx = (txIdx + 1) % TX_BUF_CNT;
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result = rtx.txbd[txIdx].status & TXBD_STATS;
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return result;
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}
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static int tsec_recv(struct eth_device* dev)
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{
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int length;
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tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
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while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
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length = rtx.rxbd[rxIdx].length;
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/* Send the packet up if there were no errors */
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if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
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NetReceive(NetRxPackets[rxIdx], length - 4);
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}
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rtx.rxbd[rxIdx].length = 0;
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/* Set the wrap bit if this is the last element in the list */
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rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
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rxIdx = (rxIdx + 1) % PKTBUFSRX;
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}
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if(regs->ievent&IEVENT_BSY) {
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regs->ievent = IEVENT_BSY;
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regs->rstat = RSTAT_CLEAR_RHALT;
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}
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return -1;
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}
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static void tsec_halt(struct eth_device* dev)
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{
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tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
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regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
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regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
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while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
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regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
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}
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#endif /* CONFIG_TSEC_ENET */
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