upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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565 lines
14 KiB
565 lines
14 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Tegra20 Clock control functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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#include <div64.h>
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#include <fdtdec.h>
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/*
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* Clock types that we can use as a source. The Tegra20 has muxes for the
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* peripheral clocks, and in most cases there are four options for the clock
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* source. This gives us a clock 'type' and exploits what commonality exists
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* in the device.
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*
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* Letters are obvious, except for T which means CLK_M, and S which means the
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* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
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* datasheet) and PLL_M are different things. The former is the basic
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* clock supplied to the SOC from an external oscillator. The latter is the
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* memory clock PLL.
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*
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* See definitions in clock_id in the header file.
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*/
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enum clock_type_id {
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CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
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CLOCK_TYPE_MCPA, /* and so on */
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CLOCK_TYPE_MCPT,
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CLOCK_TYPE_PCM,
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CLOCK_TYPE_PCMT,
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CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
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CLOCK_TYPE_PCXTS,
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CLOCK_TYPE_PDCT,
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CLOCK_TYPE_COUNT,
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CLOCK_TYPE_NONE = -1, /* invalid clock type */
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};
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enum {
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CLOCK_MAX_MUX = 4 /* number of source options for each clock */
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};
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/*
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* Clock source mux for each clock type. This just converts our enum into
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* a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
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* is special as it has 5 sources. Since it also has a different number of
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* bits in its register for the source, we just handle it with a special
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* case in the code.
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*/
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#define CLK(x) CLOCK_ID_ ## x
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static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
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{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
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{ CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
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{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
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};
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/*
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* Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
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* not in the header file since it is for purely internal use - we want
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* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
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* confusion bewteen PERIPH_ID_... and PERIPHC_...
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*
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* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
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* confusing.
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*
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* Note to SOC vendors: perhaps define a unified numbering for peripherals and
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* use it for reset, clock enable, clock source/divider and even pinmuxing
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* if you can.
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*/
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enum periphc_internal_id {
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/* 0x00 */
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PERIPHC_I2S1,
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PERIPHC_I2S2,
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PERIPHC_SPDIF_OUT,
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PERIPHC_SPDIF_IN,
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PERIPHC_PWM,
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PERIPHC_SPI1,
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PERIPHC_SPI2,
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PERIPHC_SPI3,
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/* 0x08 */
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PERIPHC_XIO,
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PERIPHC_I2C1,
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PERIPHC_DVC_I2C,
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PERIPHC_TWC,
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PERIPHC_0c,
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PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
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PERIPHC_DISP1,
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PERIPHC_DISP2,
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/* 0x10 */
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PERIPHC_CVE,
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PERIPHC_IDE0,
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PERIPHC_VI,
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PERIPHC_1c,
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PERIPHC_SDMMC1,
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PERIPHC_SDMMC2,
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PERIPHC_G3D,
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PERIPHC_G2D,
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/* 0x18 */
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PERIPHC_NDFLASH,
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PERIPHC_SDMMC4,
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PERIPHC_VFIR,
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PERIPHC_EPP,
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PERIPHC_MPE,
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PERIPHC_MIPI,
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PERIPHC_UART1,
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PERIPHC_UART2,
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/* 0x20 */
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PERIPHC_HOST1X,
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PERIPHC_21,
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PERIPHC_TVO,
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PERIPHC_HDMI,
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PERIPHC_24,
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PERIPHC_TVDAC,
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PERIPHC_I2C2,
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PERIPHC_EMC,
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/* 0x28 */
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PERIPHC_UART3,
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PERIPHC_29,
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PERIPHC_VI_SENSOR,
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PERIPHC_2b,
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PERIPHC_2c,
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PERIPHC_SPI4,
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PERIPHC_I2C3,
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PERIPHC_SDMMC3,
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/* 0x30 */
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PERIPHC_UART4,
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PERIPHC_UART5,
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PERIPHC_VDE,
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PERIPHC_OWR,
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PERIPHC_NOR,
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PERIPHC_CSITE,
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PERIPHC_COUNT,
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PERIPHC_NONE = -1,
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};
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/*
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* Clock type for each peripheral clock source. We put the name in each
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* record just so it is easy to match things up
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*/
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#define TYPE(name, type) type
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static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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/* 0x00 */
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TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
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TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
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TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
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/* 0x08 */
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TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
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/* 0x10 */
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TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
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/* 0x18 */
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TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
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/* 0x20 */
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TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
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/* 0x28 */
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TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
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/* 0x30 */
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TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
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};
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/*
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* This array translates a periph_id to a periphc_internal_id
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*
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* Not present/matched up:
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* uint vi_sensor; _VI_SENSOR_0, 0x1A8
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* SPDIF - which is both 0x08 and 0x0c
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*
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*/
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#define NONE(name) (-1)
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#define OFFSET(name, value) PERIPHC_ ## name
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static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
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/* Low word: 31:0 */
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NONE(CPU),
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NONE(RESERVED1),
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NONE(RESERVED2),
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NONE(AC97),
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NONE(RTC),
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NONE(TMR),
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PERIPHC_UART1,
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PERIPHC_UART2, /* and vfir 0x68 */
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/* 0x08 */
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NONE(GPIO),
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PERIPHC_SDMMC2,
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NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
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PERIPHC_I2S1,
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PERIPHC_I2C1,
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PERIPHC_NDFLASH,
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PERIPHC_SDMMC1,
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PERIPHC_SDMMC4,
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/* 0x10 */
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PERIPHC_TWC,
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PERIPHC_PWM,
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PERIPHC_I2S2,
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PERIPHC_EPP,
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PERIPHC_VI,
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PERIPHC_G2D,
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NONE(USBD),
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NONE(ISP),
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/* 0x18 */
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PERIPHC_G3D,
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PERIPHC_IDE0,
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PERIPHC_DISP2,
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PERIPHC_DISP1,
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PERIPHC_HOST1X,
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NONE(VCP),
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NONE(RESERVED30),
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NONE(CACHE2),
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/* Middle word: 63:32 */
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NONE(MEM),
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NONE(AHBDMA),
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NONE(APBDMA),
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NONE(RESERVED35),
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NONE(KBC),
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NONE(STAT_MON),
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NONE(PMC),
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NONE(FUSE),
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/* 0x28 */
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NONE(KFUSE),
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NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
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PERIPHC_NOR,
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PERIPHC_SPI1,
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PERIPHC_SPI2,
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PERIPHC_XIO,
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PERIPHC_SPI3,
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PERIPHC_DVC_I2C,
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/* 0x30 */
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NONE(DSI),
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PERIPHC_TVO, /* also CVE 0x40 */
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PERIPHC_MIPI,
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PERIPHC_HDMI,
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PERIPHC_CSITE,
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PERIPHC_TVDAC,
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PERIPHC_I2C2,
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PERIPHC_UART3,
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/* 0x38 */
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NONE(RESERVED56),
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PERIPHC_EMC,
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NONE(USB2),
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NONE(USB3),
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PERIPHC_MPE,
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PERIPHC_VDE,
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NONE(BSEA),
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NONE(BSEV),
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/* Upper word 95:64 */
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NONE(SPEEDO),
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PERIPHC_UART4,
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PERIPHC_UART5,
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PERIPHC_I2C3,
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PERIPHC_SPI4,
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PERIPHC_SDMMC3,
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NONE(PCIE),
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PERIPHC_OWR,
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/* 0x48 */
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NONE(AFI),
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NONE(CORESIGHT),
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NONE(RESERVED74),
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NONE(AVPUCQ),
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NONE(RESERVED76),
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NONE(RESERVED77),
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NONE(RESERVED78),
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NONE(RESERVED79),
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/* 0x50 */
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NONE(RESERVED80),
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NONE(RESERVED81),
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NONE(RESERVED82),
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NONE(RESERVED83),
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NONE(IRAMA),
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NONE(IRAMB),
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NONE(IRAMC),
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NONE(IRAMD),
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/* 0x58 */
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NONE(CRAM2),
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};
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/*
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* Get the oscillator frequency, from the corresponding hardware configuration
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* field. T20 has 4 frequencies that it supports.
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*/
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enum clock_osc_freq clock_get_osc_freq(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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reg = readl(&clkrst->crc_osc_ctrl);
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return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
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}
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/* Returns a pointer to the clock source register for a peripheral */
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u32 *get_periph_source_reg(enum periph_id periph_id)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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enum periphc_internal_id internal_id;
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assert(clock_periph_id_isvalid(periph_id));
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internal_id = periph_id_to_internal_id[periph_id];
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assert(internal_id != -1);
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return &clkrst->crc_clk_src[internal_id];
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}
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/**
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* Given a peripheral ID and the required source clock, this returns which
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* value should be programmed into the source mux for that peripheral.
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*
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* There is special code here to handle the one source type with 5 sources.
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*
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* @param periph_id peripheral to start
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* @param source PLL id of required parent clock
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* @param mux_bits Set to number of bits in mux register: 2 or 4
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* @param divider_bits Set to number of divider bits (8 or 16)
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* @return mux value (0-4, or -1 if not found)
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*/
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int get_periph_clock_source(enum periph_id periph_id,
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enum clock_id parent, int *mux_bits, int *divider_bits)
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{
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enum clock_type_id type;
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enum periphc_internal_id internal_id;
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int mux;
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assert(clock_periph_id_isvalid(periph_id));
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internal_id = periph_id_to_internal_id[periph_id];
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assert(periphc_internal_id_isvalid(internal_id));
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type = clock_periph_type[internal_id];
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assert(clock_type_id_isvalid(type));
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/*
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* Special cases here for the clock with a 4-bit source mux and I2C
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* with its 16-bit divisor
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*/
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if (type == CLOCK_TYPE_PCXTS)
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*mux_bits = 4;
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else
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*mux_bits = 2;
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if (type == CLOCK_TYPE_PCMT16)
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*divider_bits = 16;
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else
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*divider_bits = 8;
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for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
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if (clock_source[type][mux] == parent)
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return mux;
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/*
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* Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
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* which is not in our table. If not, then they are asking for a
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* source which this peripheral can't access through its mux.
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*/
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assert(type == CLOCK_TYPE_PCXTS);
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assert(parent == CLOCK_ID_SFROM32KHZ);
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if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
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return 4; /* mux value for this clock */
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/* if we get here, either us or the caller has made a mistake */
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printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
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parent);
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return -1;
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}
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void clock_set_enable(enum periph_id periph_id, int enable)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
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u32 reg;
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/* Enable/disable the clock to this peripheral */
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assert(clock_periph_id_isvalid(periph_id));
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reg = readl(clk);
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if (enable)
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reg |= PERIPH_MASK(periph_id);
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else
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reg &= ~PERIPH_MASK(periph_id);
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writel(reg, clk);
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}
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|
|
|
void reset_set_enable(enum periph_id periph_id, int enable)
|
|
{
|
|
struct clk_rst_ctlr *clkrst =
|
|
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
|
u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
|
|
u32 reg;
|
|
|
|
/* Enable/disable reset to the peripheral */
|
|
assert(clock_periph_id_isvalid(periph_id));
|
|
reg = readl(reset);
|
|
if (enable)
|
|
reg |= PERIPH_MASK(periph_id);
|
|
else
|
|
reg &= ~PERIPH_MASK(periph_id);
|
|
writel(reg, reset);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_CONTROL
|
|
/*
|
|
* Convert a device tree clock ID to our peripheral ID. They are mostly
|
|
* the same but we are very cautious so we check that a valid clock ID is
|
|
* provided.
|
|
*
|
|
* @param clk_id Clock ID according to tegra20 device tree binding
|
|
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
|
|
*/
|
|
enum periph_id clk_id_to_periph_id(int clk_id)
|
|
{
|
|
if (clk_id > PERIPH_ID_COUNT)
|
|
return PERIPH_ID_NONE;
|
|
|
|
switch (clk_id) {
|
|
case PERIPH_ID_RESERVED1:
|
|
case PERIPH_ID_RESERVED2:
|
|
case PERIPH_ID_RESERVED30:
|
|
case PERIPH_ID_RESERVED35:
|
|
case PERIPH_ID_RESERVED56:
|
|
case PERIPH_ID_RESERVED74:
|
|
case PERIPH_ID_RESERVED76:
|
|
case PERIPH_ID_RESERVED77:
|
|
case PERIPH_ID_RESERVED78:
|
|
case PERIPH_ID_RESERVED79:
|
|
case PERIPH_ID_RESERVED80:
|
|
case PERIPH_ID_RESERVED81:
|
|
case PERIPH_ID_RESERVED82:
|
|
case PERIPH_ID_RESERVED83:
|
|
case PERIPH_ID_RESERVED91:
|
|
return PERIPH_ID_NONE;
|
|
default:
|
|
return clk_id;
|
|
}
|
|
}
|
|
#endif /* CONFIG_OF_CONTROL */
|
|
|
|
void clock_early_init(void)
|
|
{
|
|
/*
|
|
* PLLP output frequency set to 216MHz
|
|
* PLLC output frequency set to 600Mhz
|
|
*
|
|
* TODO: Can we calculate these values instead of hard-coding?
|
|
*/
|
|
switch (clock_get_osc_freq()) {
|
|
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
|
|
break;
|
|
|
|
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
|
|
clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
|
|
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
|
|
break;
|
|
case CLOCK_OSC_FREQ_19_2:
|
|
default:
|
|
/*
|
|
* These are not supported. It is too early to print a
|
|
* message and the UART likely won't work anyway due to the
|
|
* oscillator being wrong.
|
|
*/
|
|
break;
|
|
}
|
|
}
|
|
|
|
void arch_timer_init(void)
|
|
{
|
|
}
|
|
|