upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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671 lines
17 KiB
671 lines
17 KiB
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <net.h>
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#include <hwconfig.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/fsl_dtsec.h>
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#include <asm/fsl_tgec.h>
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#include "fm.h"
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static struct eth_device *devlist[NUM_FM_PORTS];
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static int num_controllers;
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
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#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
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TBIANA_FULL_DUPLEX)
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#define TBIANA_SGMII_ACK 0x4001
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#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
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TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
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/* Configure the TBI for SGMII operation */
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void dtsec_configure_serdes(struct fm_eth *priv)
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{
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struct dtsec *regs = priv->mac->base;
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struct tsec_mii_mng *phyregs = priv->mac->phyregs;
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/*
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* Access TBI PHY registers at given TSEC register offset as
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* opposed to the register offset used for external PHY accesses
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*/
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tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
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TBICON_CLK_SELECT);
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tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
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TBIANA_SGMII_ACK);
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tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
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TBI_CR, TBICR_SETTINGS);
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}
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static void dtsec_init_phy(struct eth_device *dev)
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{
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struct fm_eth *fm_eth = dev->priv;
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struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
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/* Assign a Physical address to the TBI */
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out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
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if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
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dtsec_configure_serdes(fm_eth);
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}
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static int tgec_is_fibre(struct eth_device *dev)
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{
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struct fm_eth *fm = dev->priv;
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char phyopt[20];
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sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
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return hwconfig_arg_cmp(phyopt, "xfi");
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}
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#endif
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static u16 muram_readw(u16 *addr)
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{
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u32 base = (u32)addr & ~0x3;
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u32 val32 = *(u32 *)base;
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int byte_pos;
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u16 ret;
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byte_pos = (u32)addr & 0x3;
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if (byte_pos)
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ret = (u16)(val32 & 0x0000ffff);
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else
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ret = (u16)((val32 & 0xffff0000) >> 16);
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return ret;
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}
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static void muram_writew(u16 *addr, u16 val)
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{
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u32 base = (u32)addr & ~0x3;
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u32 org32 = *(u32 *)base;
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u32 val32;
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int byte_pos;
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byte_pos = (u32)addr & 0x3;
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if (byte_pos)
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val32 = (org32 & 0xffff0000) | val;
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else
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val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
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*(u32 *)base = val32;
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}
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static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
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{
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int timeout = 1000000;
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clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
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/* wait until the rx port is not busy */
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while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
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;
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}
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static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
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{
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/* set BMI to independent mode, Rx port disable */
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out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
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/* clear FOF in IM case */
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out_be32(&rx_port->fmbm_rim, 0);
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/* Rx frame next engine -RISC */
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out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
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/* Rx command attribute - no order, MR[3] = 1 */
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clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
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setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
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/* enable Rx statistic counters */
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out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
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/* disable Rx performance counters */
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out_be32(&rx_port->fmbm_rpc, 0);
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}
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static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
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{
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int timeout = 1000000;
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clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
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/* wait until the tx port is not busy */
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while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
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;
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}
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static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
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{
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/* set BMI to independent mode, Tx port disable */
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out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
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/* Tx frame next engine -RISC */
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out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
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out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
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/* Tx command attribute - no order, MR[3] = 1 */
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clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
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setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
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/* enable Tx statistic counters */
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out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
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/* disable Tx performance counters */
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out_be32(&tx_port->fmbm_tpc, 0);
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}
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static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
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{
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struct fm_port_global_pram *pram;
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u32 pram_page_offset;
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void *rx_bd_ring_base;
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void *rx_buf_pool;
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struct fm_port_bd *rxbd;
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struct fm_port_qd *rxqd;
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struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
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int i;
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/* alloc global parameter ram at MURAM */
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pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
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FM_PRAM_SIZE, FM_PRAM_ALIGN);
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fm_eth->rx_pram = pram;
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/* parameter page offset to MURAM */
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pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
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/* enable global mode- snooping data buffers and BDs */
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pram->mode = PRAM_MODE_GLOBAL;
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/* init the Rx queue descriptor pionter */
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pram->rxqd_ptr = pram_page_offset + 0x20;
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/* set the max receive buffer length, power of 2 */
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muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
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/* alloc Rx buffer descriptors from main memory */
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rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
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* RX_BD_RING_SIZE);
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if (!rx_bd_ring_base)
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return 0;
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memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
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* RX_BD_RING_SIZE);
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/* alloc Rx buffer from main memory */
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rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
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if (!rx_buf_pool)
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return 0;
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memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
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/* save them to fm_eth */
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fm_eth->rx_bd_ring = rx_bd_ring_base;
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fm_eth->cur_rxbd = rx_bd_ring_base;
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fm_eth->rx_buf = rx_buf_pool;
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/* init Rx BDs ring */
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rxbd = (struct fm_port_bd *)rx_bd_ring_base;
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for (i = 0; i < RX_BD_RING_SIZE; i++) {
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rxbd->status = RxBD_EMPTY;
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rxbd->len = 0;
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rxbd->buf_ptr_hi = 0;
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rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
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rxbd++;
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}
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/* set the Rx queue descriptor */
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rxqd = &pram->rxqd;
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muram_writew(&rxqd->gen, 0);
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muram_writew(&rxqd->bd_ring_base_hi, 0);
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rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
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muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
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* RX_BD_RING_SIZE);
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muram_writew(&rxqd->offset_in, 0);
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muram_writew(&rxqd->offset_out, 0);
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/* set IM parameter ram pointer to Rx Frame Queue ID */
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out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
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return 1;
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}
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static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
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{
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struct fm_port_global_pram *pram;
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u32 pram_page_offset;
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void *tx_bd_ring_base;
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struct fm_port_bd *txbd;
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struct fm_port_qd *txqd;
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struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
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int i;
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/* alloc global parameter ram at MURAM */
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pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
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FM_PRAM_SIZE, FM_PRAM_ALIGN);
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fm_eth->tx_pram = pram;
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/* parameter page offset to MURAM */
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pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
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/* enable global mode- snooping data buffers and BDs */
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pram->mode = PRAM_MODE_GLOBAL;
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/* init the Tx queue descriptor pionter */
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pram->txqd_ptr = pram_page_offset + 0x40;
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/* alloc Tx buffer descriptors from main memory */
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tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
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* TX_BD_RING_SIZE);
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if (!tx_bd_ring_base)
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return 0;
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memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
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* TX_BD_RING_SIZE);
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/* save it to fm_eth */
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fm_eth->tx_bd_ring = tx_bd_ring_base;
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fm_eth->cur_txbd = tx_bd_ring_base;
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/* init Tx BDs ring */
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txbd = (struct fm_port_bd *)tx_bd_ring_base;
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for (i = 0; i < TX_BD_RING_SIZE; i++) {
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txbd->status = TxBD_LAST;
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txbd->len = 0;
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txbd->buf_ptr_hi = 0;
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txbd->buf_ptr_lo = 0;
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}
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/* set the Tx queue decriptor */
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txqd = &pram->txqd;
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muram_writew(&txqd->bd_ring_base_hi, 0);
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txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
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muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
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* TX_BD_RING_SIZE);
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muram_writew(&txqd->offset_in, 0);
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muram_writew(&txqd->offset_out, 0);
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/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
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out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
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return 1;
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}
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static int fm_eth_init(struct fm_eth *fm_eth)
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{
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if (!fm_eth_rx_port_parameter_init(fm_eth))
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return 0;
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if (!fm_eth_tx_port_parameter_init(fm_eth))
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return 0;
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return 1;
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}
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static int fm_eth_startup(struct fm_eth *fm_eth)
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{
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struct fsl_enet_mac *mac;
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mac = fm_eth->mac;
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/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
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if (!fm_eth_init(fm_eth))
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return 0;
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/* setup the MAC controller */
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mac->init_mac(mac);
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/* For some reason we need to set SPEED_100 */
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if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode)
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mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
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/* init bmi rx port, IM mode and disable */
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bmi_rx_port_init(fm_eth->rx_port);
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/* init bmi tx port, IM mode and disable */
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bmi_tx_port_init(fm_eth->tx_port);
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return 1;
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}
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static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
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{
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struct fm_port_global_pram *pram;
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pram = fm_eth->tx_pram;
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/* graceful stop transmission of frames */
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pram->mode |= PRAM_MODE_GRACEFUL_STOP;
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sync();
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}
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static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
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{
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struct fm_port_global_pram *pram;
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pram = fm_eth->tx_pram;
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/* re-enable transmission of frames */
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pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
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sync();
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}
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static int fm_eth_open(struct eth_device *dev, bd_t *bd)
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{
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struct fm_eth *fm_eth;
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struct fsl_enet_mac *mac;
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fm_eth = (struct fm_eth *)dev->priv;
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mac = fm_eth->mac;
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/* setup the MAC address */
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if (dev->enetaddr[0] & 0x01) {
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printf("%s: MacAddress is multcast address\n", __func__);
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return 1;
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}
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mac->set_mac_addr(mac, dev->enetaddr);
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/* enable bmi Rx port */
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setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
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/* enable MAC rx/tx port */
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mac->enable_mac(mac);
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/* enable bmi Tx port */
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setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
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/* re-enable transmission of frame */
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fmc_tx_port_graceful_stop_disable(fm_eth);
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#ifdef CONFIG_PHYLIB
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phy_startup(fm_eth->phydev);
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#else
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fm_eth->phydev->speed = SPEED_1000;
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fm_eth->phydev->link = 1;
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fm_eth->phydev->duplex = DUPLEX_FULL;
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#endif
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/* set the MAC-PHY mode */
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mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
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if (!fm_eth->phydev->link)
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printf("%s: No link.\n", fm_eth->phydev->dev->name);
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return fm_eth->phydev->link ? 0 : -1;
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}
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static void fm_eth_halt(struct eth_device *dev)
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{
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struct fm_eth *fm_eth;
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struct fsl_enet_mac *mac;
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fm_eth = (struct fm_eth *)dev->priv;
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mac = fm_eth->mac;
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/* graceful stop the transmission of frames */
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fmc_tx_port_graceful_stop_enable(fm_eth);
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/* disable bmi Tx port */
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bmi_tx_port_disable(fm_eth->tx_port);
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/* disable MAC rx/tx port */
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mac->disable_mac(mac);
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/* disable bmi Rx port */
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bmi_rx_port_disable(fm_eth->rx_port);
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phy_shutdown(fm_eth->phydev);
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}
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static int fm_eth_send(struct eth_device *dev, volatile void *buf, int len)
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{
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struct fm_eth *fm_eth;
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struct fm_port_global_pram *pram;
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struct fm_port_bd *txbd, *txbd_base;
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u16 offset_in;
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int i;
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fm_eth = (struct fm_eth *)dev->priv;
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pram = fm_eth->tx_pram;
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txbd = fm_eth->cur_txbd;
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/* find one empty TxBD */
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for (i = 0; txbd->status & TxBD_READY; i++) {
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udelay(100);
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if (i > 0x1000) {
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printf("%s: Tx buffer not ready\n", dev->name);
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return 0;
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}
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}
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/* setup TxBD */
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txbd->buf_ptr_hi = 0;
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txbd->buf_ptr_lo = (u32)buf;
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txbd->len = len;
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sync();
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txbd->status = TxBD_READY | TxBD_LAST;
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sync();
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/* update TxQD, let RISC to send the packet */
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offset_in = muram_readw(&pram->txqd.offset_in);
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offset_in += sizeof(struct fm_port_bd);
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if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
|
|
offset_in = 0;
|
|
muram_writew(&pram->txqd.offset_in, offset_in);
|
|
sync();
|
|
|
|
/* wait for buffer to be transmitted */
|
|
for (i = 0; txbd->status & TxBD_READY; i++) {
|
|
udelay(100);
|
|
if (i > 0x10000) {
|
|
printf("%s: Tx error\n", dev->name);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* advance the TxBD */
|
|
txbd++;
|
|
txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
|
|
if (txbd >= (txbd_base + TX_BD_RING_SIZE))
|
|
txbd = txbd_base;
|
|
/* update current txbd */
|
|
fm_eth->cur_txbd = (void *)txbd;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int fm_eth_recv(struct eth_device *dev)
|
|
{
|
|
struct fm_eth *fm_eth;
|
|
struct fm_port_global_pram *pram;
|
|
struct fm_port_bd *rxbd, *rxbd_base;
|
|
u16 status, len;
|
|
u8 *data;
|
|
u16 offset_out;
|
|
|
|
fm_eth = (struct fm_eth *)dev->priv;
|
|
pram = fm_eth->rx_pram;
|
|
rxbd = fm_eth->cur_rxbd;
|
|
status = rxbd->status;
|
|
|
|
while (!(status & RxBD_EMPTY)) {
|
|
if (!(status & RxBD_ERROR)) {
|
|
data = (u8 *)rxbd->buf_ptr_lo;
|
|
len = rxbd->len;
|
|
NetReceive(data, len);
|
|
} else {
|
|
printf("%s: Rx error\n", dev->name);
|
|
return 0;
|
|
}
|
|
|
|
/* clear the RxBDs */
|
|
rxbd->status = RxBD_EMPTY;
|
|
rxbd->len = 0;
|
|
sync();
|
|
|
|
/* advance RxBD */
|
|
rxbd++;
|
|
rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
|
|
if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
|
|
rxbd = rxbd_base;
|
|
/* read next status */
|
|
status = rxbd->status;
|
|
|
|
/* update RxQD */
|
|
offset_out = muram_readw(&pram->rxqd.offset_out);
|
|
offset_out += sizeof(struct fm_port_bd);
|
|
if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
|
|
offset_out = 0;
|
|
muram_writew(&pram->rxqd.offset_out, offset_out);
|
|
sync();
|
|
}
|
|
fm_eth->cur_rxbd = (void *)rxbd;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
|
|
{
|
|
struct fsl_enet_mac *mac;
|
|
int num;
|
|
void *base, *phyregs = NULL;
|
|
|
|
num = fm_eth->num;
|
|
|
|
/* Get the mac registers base address */
|
|
if (fm_eth->type == FM_ETH_1G_E) {
|
|
base = ®->mac_1g[num].fm_dtesc;
|
|
phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
|
|
} else {
|
|
base = ®->mac_10g[num].fm_10gec;
|
|
phyregs = ®->mac_10g[num].fm_10gec_mdio;
|
|
}
|
|
|
|
/* alloc mac controller */
|
|
mac = malloc(sizeof(struct fsl_enet_mac));
|
|
if (!mac)
|
|
return 0;
|
|
memset(mac, 0, sizeof(struct fsl_enet_mac));
|
|
|
|
/* save the mac to fm_eth struct */
|
|
fm_eth->mac = mac;
|
|
|
|
if (fm_eth->type == FM_ETH_1G_E)
|
|
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
|
|
else
|
|
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int init_phy(struct eth_device *dev)
|
|
{
|
|
struct fm_eth *fm_eth = dev->priv;
|
|
struct phy_device *phydev = NULL;
|
|
u32 supported;
|
|
|
|
#ifdef CONFIG_PHYLIB
|
|
if (fm_eth->type == FM_ETH_1G_E)
|
|
dtsec_init_phy(dev);
|
|
|
|
if (fm_eth->bus) {
|
|
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
|
|
fm_eth->enet_if);
|
|
}
|
|
|
|
if (!phydev) {
|
|
printf("Failed to connect\n");
|
|
return -1;
|
|
}
|
|
|
|
if (fm_eth->type == FM_ETH_1G_E) {
|
|
supported = (SUPPORTED_10baseT_Half |
|
|
SUPPORTED_10baseT_Full |
|
|
SUPPORTED_100baseT_Half |
|
|
SUPPORTED_100baseT_Full |
|
|
SUPPORTED_1000baseT_Full);
|
|
} else {
|
|
supported = SUPPORTED_10000baseT_Full;
|
|
|
|
if (tgec_is_fibre(dev))
|
|
phydev->port = PORT_FIBRE;
|
|
}
|
|
|
|
phydev->supported &= supported;
|
|
phydev->advertising = phydev->supported;
|
|
|
|
fm_eth->phydev = phydev;
|
|
|
|
phy_config(phydev);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
|
|
{
|
|
struct eth_device *dev;
|
|
struct fm_eth *fm_eth;
|
|
int i, num = info->num;
|
|
|
|
/* alloc eth device */
|
|
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
|
if (!dev)
|
|
return 0;
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
|
|
/* alloc the FMan ethernet private struct */
|
|
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
|
|
if (!fm_eth)
|
|
return 0;
|
|
memset(fm_eth, 0, sizeof(struct fm_eth));
|
|
|
|
/* save off some things we need from the info struct */
|
|
fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
|
|
fm_eth->num = num;
|
|
fm_eth->type = info->type;
|
|
|
|
fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
|
|
fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
|
|
|
|
/* set the ethernet max receive length */
|
|
fm_eth->max_rx_len = MAX_RXBUF_LEN;
|
|
|
|
/* init global mac structure */
|
|
if (!fm_eth_init_mac(fm_eth, reg))
|
|
return 0;
|
|
|
|
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
|
|
if (fm_eth->type == FM_ETH_1G_E)
|
|
sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
|
|
else
|
|
sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
|
|
|
|
devlist[num_controllers++] = dev;
|
|
dev->iobase = 0;
|
|
dev->priv = (void *)fm_eth;
|
|
dev->init = fm_eth_open;
|
|
dev->halt = fm_eth_halt;
|
|
dev->send = fm_eth_send;
|
|
dev->recv = fm_eth_recv;
|
|
fm_eth->dev = dev;
|
|
fm_eth->bus = info->bus;
|
|
fm_eth->phyaddr = info->phy_addr;
|
|
fm_eth->enet_if = info->enet_if;
|
|
|
|
/* startup the FM im */
|
|
if (!fm_eth_startup(fm_eth))
|
|
return 0;
|
|
|
|
if (init_phy(dev))
|
|
return 0;
|
|
|
|
/* clear the ethernet address */
|
|
for (i = 0; i < 6; i++)
|
|
dev->enetaddr[i] = 0;
|
|
eth_register(dev);
|
|
|
|
return 1;
|
|
}
|
|
|