upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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326 lines
8.8 KiB
326 lines
8.8 KiB
/*
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* (C) Copyright 2014
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <input.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <pwm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define DISP_PAD_CTRL (0x10)
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#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
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#if (CONFIG_SYS_BOARD_VERSION == 1)
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#include "./aristainetos-v1.c"
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#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
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#include "./aristainetos-v2.c"
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#endif
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
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.gp = IMX_GPIO_NR(5, 27)
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},
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.sda = {
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.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
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.gp = IMX_GPIO_NR(5, 26)
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}
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};
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC1_BASE_ADDR},
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{USDHC2_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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#if (CONFIG_SYS_BOARD_VERSION == 2)
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/*
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* usdhc2 has a levelshifter on the carrier board Rev. DV1,
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* that will automatically detect the driving direction.
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* During initialisation this isn't working correctly,
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* which causes DAT3 to be driven low towards the SD-card.
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* This causes a SD-card enetring the SPI-Mode
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* and therefore getting inaccessible until next power cycle.
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* As workaround we drive the DAT3 line as GPIO and set it high.
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* This makes usdhc2 unusable in u-boot, but works for the
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* initialisation in Linux
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*/
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imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
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MUX_PAD_CTRL(NO_PAD_CTRL));
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gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
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#endif
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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}
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#endif
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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struct display_info_t const displays[] = {
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{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = NULL,
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.enable = enable_lvds,
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.mode = {
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.name = "lb07wv8",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30066,
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.left_margin = 88,
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.right_margin = 88,
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.upper_margin = 20,
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.lower_margin = 20,
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.hsync_len = 80,
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.vsync_len = 5,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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}
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}
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#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
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, {
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = NULL,
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.enable = enable_spi_display,
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.mode = {
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.name = "lg4573",
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.refresh = 57,
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.xres = 480,
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.yres = 800,
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.pixclock = 37037,
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.left_margin = 59,
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.right_margin = 10,
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.upper_margin = 15,
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.lower_margin = 15,
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.hsync_len = 10,
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.vsync_len = 15,
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.sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
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FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED
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}
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}
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#endif
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};
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size_t display_count = ARRAY_SIZE(displays);
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/* no console on this board */
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int board_cfb_skip(void)
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{
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return 1;
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}
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iomux_v3_cfg_t nfc_pads[] = {
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(nfc_pads,
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ARRAY_SIZE(nfc_pads));
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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int board_init(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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setup_spi();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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&i2c_pad_info1);
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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&i2c_pad_info2);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
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&i2c_pad_info3);
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setup_i2c4();
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/* SPI NOR Flash read only */
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gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
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gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
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gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
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setup_board_gpio();
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setup_gpmi_nand();
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setup_board_spi();
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/* GPIO_1 for USB_OTG_ID */
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clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
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imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: %s\n", CONFIG_BOARDNAME);
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return 0;
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}
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#ifdef CONFIG_USB_EHCI_MX6
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int board_ehci_hcd_init(int port)
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{
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int ret;
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ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
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if (!ret)
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gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
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ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
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if (!ret)
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gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
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return 0;
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}
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int board_ehci_power(int port, int on)
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{
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if (port)
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gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
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else
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gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
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return 0;
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}
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#endif
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