upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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416 lines
10 KiB
416 lines
10 KiB
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fdt_support.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <fsl_dtsec.h>
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#include <malloc.h>
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#include <asm/arch/fsl_serdes.h>
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#include "../common/qixis.h"
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#include "../common/fman.h"
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#include "ls1046aqds_qixis.h"
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#define EMI_NONE 0xFF
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#define EMI1_RGMII1 0
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#define EMI1_RGMII2 1
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#define EMI1_SLOT1 2
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#define EMI1_SLOT2 3
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#define EMI1_SLOT4 4
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static int mdio_mux[NUM_FM_PORTS];
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static const char * const mdio_names[] = {
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"LS1046AQDS_MDIO_RGMII1",
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"LS1046AQDS_MDIO_RGMII2",
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"LS1046AQDS_MDIO_SLOT1",
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"LS1046AQDS_MDIO_SLOT2",
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"LS1046AQDS_MDIO_SLOT4",
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"NULL",
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};
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/* Map SerDes 1 & 2 lanes to default slot. */
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static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
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static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name;
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if (muxval > EMI1_SLOT4)
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return NULL;
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name = ls1046aqds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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struct ls1046aqds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static void ls1046aqds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval < 7) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct ls1046aqds_mdio *priv = bus->priv;
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ls1046aqds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct ls1046aqds_mdio *priv = bus->priv;
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ls1046aqds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad,
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regnum, value);
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}
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static int ls1046aqds_mdio_reset(struct mii_dev *bus)
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{
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struct ls1046aqds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
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{
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struct ls1046aqds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate ls1046aqds MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate ls1046aqds private data\n");
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free(bus);
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return -1;
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}
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bus->read = ls1046aqds_mdio_read;
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bus->write = ls1046aqds_mdio_write;
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bus->reset = ls1046aqds_mdio_reset;
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sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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struct fixed_link f_link;
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if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
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switch (port) {
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case FM1_DTSEC9:
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fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1");
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break;
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case FM1_DTSEC10:
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fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2");
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break;
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case FM1_DTSEC5:
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fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3");
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break;
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case FM1_DTSEC6:
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fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4");
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break;
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case FM1_DTSEC2:
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fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1");
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break;
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default:
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break;
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}
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
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/* 2.5G SGMII interface */
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f_link.phy_id = cpu_to_fdt32(port);
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f_link.duplex = cpu_to_fdt32(1);
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f_link.link_speed = cpu_to_fdt32(1000);
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f_link.pause = 0;
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f_link.asym_pause = 0;
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/* no PHY for 2.5G SGMII on QDS */
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fdt_delprop(fdt, offset, "phy-handle");
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fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
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fdt_setprop_string(fdt, offset, "phy-connection-type",
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"sgmii-2500");
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
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switch (port) {
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case FM1_DTSEC1:
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fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4");
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break;
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case FM1_DTSEC5:
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fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2");
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break;
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case FM1_DTSEC6:
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fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1");
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break;
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case FM1_DTSEC10:
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fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3");
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break;
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default:
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break;
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}
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fdt_delprop(fdt, offset, "phy-connection-type");
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fdt_setprop_string(fdt, offset, "phy-connection-type",
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"qsgmii");
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
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(port == FM1_10GEC1 || port == FM1_10GEC2)) {
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/* XFI interface */
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f_link.phy_id = cpu_to_fdt32(port);
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f_link.duplex = cpu_to_fdt32(1);
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f_link.link_speed = cpu_to_fdt32(10000);
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f_link.pause = 0;
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f_link.asym_pause = 0;
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/* no PHY for XFI */
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fdt_delprop(fdt, offset, "phy-handle");
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fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
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fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int i;
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for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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switch (mdio_mux[i]) {
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case EMI1_SLOT1:
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fdt_status_okay_by_alias(fdt, "emi1_slot1");
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break;
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case EMI1_SLOT2:
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fdt_status_okay_by_alias(fdt, "emi1_slot2");
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break;
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case EMI1_SLOT4:
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fdt_status_okay_by_alias(fdt, "emi1_slot4");
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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int i, idx, lane, slot, interface;
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struct memac_mdio_info dtsec_mdio_info;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 srds_s1, srds_s2;
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u8 brdcfg12;
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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srds_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
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srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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/* Register the muxing front-ends to the MDIO buses */
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ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
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ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
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ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
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ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
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ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
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/* Set the two on-board RGMII PHY address */
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fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
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switch (srds_s1) {
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case 0x3333:
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/* SGMII on slot 1, MAC 9 */
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fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
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case 0x1333:
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case 0x2333:
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/* SGMII on slot 1, MAC 10 */
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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case 0x1133:
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case 0x2233:
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/* SGMII on slot 1, MAC 5/6 */
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fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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case 0x1040:
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case 0x2040:
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/* QSGMII on lane B, MAC 6/5/10/1 */
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fm_info_set_phy_address(FM1_DTSEC6,
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QSGMII_CARD_PORT1_PHY_ADDR_S2);
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fm_info_set_phy_address(FM1_DTSEC5,
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QSGMII_CARD_PORT2_PHY_ADDR_S2);
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fm_info_set_phy_address(FM1_DTSEC10,
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QSGMII_CARD_PORT3_PHY_ADDR_S2);
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fm_info_set_phy_address(FM1_DTSEC1,
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QSGMII_CARD_PORT4_PHY_ADDR_S2);
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break;
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case 0x3363:
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/* SGMII on slot 1, MAC 9/10 */
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fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
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case 0x1163:
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case 0x2263:
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case 0x2223:
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/* SGMII on slot 1, MAC 6 */
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fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
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break;
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default:
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printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
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srds_s1);
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break;
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}
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if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
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/* SGMII on slot 4, MAC 2 */
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fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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idx = i - FM1_DTSEC1;
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interface = fm_info_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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if (interface == PHY_INTERFACE_MODE_SGMII) {
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if (i == FM1_DTSEC5) {
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/* route lane 2 to slot1 so to have
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* one sgmii riser card supports
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* MAC5 and MAC6.
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*/
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brdcfg12 = QIXIS_READ(brdcfg[12]);
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QIXIS_WRITE(brdcfg[12],
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brdcfg12 | 0x80);
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}
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lane = serdes_get_first_lane(FSL_SRDS_1,
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SGMII_FM1_DTSEC1 + idx);
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} else {
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/* clear the bit 7 to route lane B on slot2. */
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brdcfg12 = QIXIS_READ(brdcfg[12]);
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QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
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lane = serdes_get_first_lane(FSL_SRDS_1,
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QSGMII_FM1_A);
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lane_to_slot[lane] = 2;
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}
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if (i == FM1_DTSEC2)
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lane = 5;
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if (lane < 0)
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break;
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slot = lane_to_slot[lane];
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debug("FM1@DTSEC%u expects SGMII in slot %u\n",
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idx + 1, slot);
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if (QIXIS_READ(present2) & (1 << (slot - 1)))
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fm_disable_port(i);
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switch (slot) {
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case 1:
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mdio_mux[i] = EMI1_SLOT1;
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fm_info_set_mdio(i, mii_dev_for_muxval(
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mdio_mux[i]));
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break;
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case 2:
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mdio_mux[i] = EMI1_SLOT2;
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fm_info_set_mdio(i, mii_dev_for_muxval(
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mdio_mux[i]));
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break;
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case 4:
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mdio_mux[i] = EMI1_SLOT4;
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fm_info_set_mdio(i, mii_dev_for_muxval(
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mdio_mux[i]));
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break;
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default:
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break;
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}
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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if (i == FM1_DTSEC3)
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mdio_mux[i] = EMI1_RGMII1;
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else if (i == FM1_DTSEC4)
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mdio_mux[i] = EMI1_RGMII2;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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}
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cpu_eth_init(bis);
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#endif /* CONFIG_FMAN_ENET */
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return pci_eth_init(bis);
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}
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