upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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76 lines
1.5 KiB
76 lines
1.5 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale FireEngine 5329 EVB\n");
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return 0;
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};
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int dram_init(void)
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{
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sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
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u32 dramsize, i;
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
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out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
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out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
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/* Issue PALL */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Issue LEMR */
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
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udelay(500);
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/* Issue PALL */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Perform two refresh cycles */
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
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out_be32(&sdram->ctrl,
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(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
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udelay(100);
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gd->ram_size = dramsize;
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return 0;
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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