upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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265 lines
11 KiB
265 lines
11 KiB
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Roy Zang <tie-fei.zang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MEMAC_H__
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#define __MEMAC_H__
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#include <phy.h>
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struct memac {
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/* memac general control and status registers */
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u32 res_0[2];
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u32 command_config; /* Control and configuration register */
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u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
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u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
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u32 maxfrm; /* Maximum frame length register */
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u32 res_18[5];
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u32 hashtable_ctrl; /* Hash table control register */
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u32 res_30[4];
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u32 ievent; /* Interrupt event register */
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u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
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u32 res_48;
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u32 imask; /* interrupt mask register */
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u32 res_50;
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u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
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u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
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u32 rx_pause_status; /* Receive pause status register */
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u32 res_78[2];
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u32 mac_addr[14]; /* MAC address */
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u32 lpwake_timer; /* EEE low power wakeup timer register */
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u32 sleep_timer; /* Transmit EEE Low Power Timer register */
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u32 res_c0[8];
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u32 statn_config; /* Statistics configuration register */
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u32 res_e4[7];
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/* memac statistics counter registers */
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u32 rx_eoct_l; /* Rx ethernet octests lower */
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u32 rx_eoct_u; /* Rx ethernet octests upper */
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u32 rx_oct_l; /* Rx octests lower */
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u32 rx_oct_u; /* Rx octests upper */
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u32 rx_align_err_l; /* Rx alignment error lower */
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u32 rx_align_err_u; /* Rx alignment error upper */
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u32 rx_pause_frame_l; /* Rx valid pause frame upper */
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u32 rx_pause_frame_u; /* Rx valid pause frame upper */
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u32 rx_frame_l; /* Rx frame counter lower */
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u32 rx_frame_u; /* Rx frame counter upper */
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u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
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u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
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u32 rx_vlan_l; /* Rx VLAN frame lower */
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u32 rx_vlan_u; /* Rx VLAN frame upper */
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u32 rx_err_l; /* Rx frame error lower */
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u32 rx_err_u; /* Rx frame error upper */
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u32 rx_uni_l; /* Rx unicast frame lower */
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u32 rx_uni_u; /* Rx unicast frame upper */
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u32 rx_multi_l; /* Rx multicast frame lower */
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u32 rx_multi_u; /* Rx multicast frame upper */
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u32 rx_brd_l; /* Rx broadcast frame lower */
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u32 rx_brd_u; /* Rx broadcast frame upper */
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u32 rx_drop_l; /* Rx dropped packets lower */
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u32 rx_drop_u; /* Rx dropped packets upper */
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u32 rx_pkt_l; /* Rx packets lower */
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u32 rx_pkt_u; /* Rx packets upper */
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u32 rx_undsz_l; /* Rx undersized packet lower */
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u32 rx_undsz_u; /* Rx undersized packet upper */
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u32 rx_64_l; /* Rx 64 oct packet lower */
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u32 rx_64_u; /* Rx 64 oct packet upper */
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u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
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u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
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u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
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u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
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u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
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u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
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u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
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u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
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u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
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u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
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u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
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u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
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u32 rx_oversz_l; /* Rx oversized packet lower */
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u32 rx_oversz_u; /* Rx oversized packet upper */
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u32 rx_jabber_l; /* Rx Jabber packet lower */
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u32 rx_jabber_u; /* Rx Jabber packet upper */
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u32 rx_frag_l; /* Rx Fragment packet lower */
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u32 rx_frag_u; /* Rx Fragment packet upper */
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u32 rx_cnp_l; /* Rx control packet lower */
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u32 rx_cnp_u; /* Rx control packet upper */
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u32 rx_drntp_l; /* Rx dripped not truncated packet lower */
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u32 rx_drntp_u; /* Rx dripped not truncated packet upper */
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u32 res_1d0[0xc];
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u32 tx_eoct_l; /* Tx ethernet octests lower */
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u32 tx_eoct_u; /* Tx ethernet octests upper */
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u32 tx_oct_l; /* Tx octests lower */
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u32 tx_oct_u; /* Tx octests upper */
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u32 res_210[0x2];
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u32 tx_pause_frame_l; /* Tx valid pause frame lower */
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u32 tx_pause_frame_u; /* Tx valid pause frame upper */
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u32 tx_frame_l; /* Tx frame counter lower */
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u32 tx_frame_u; /* Tx frame counter upper */
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u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */
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u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */
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u32 tx_vlan_l; /* Tx VLAN frame lower */
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u32 tx_vlan_u; /* Tx VLAN frame upper */
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u32 tx_frame_err_l; /* Tx frame error lower */
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u32 tx_frame_err_u; /* Tx frame error upper */
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u32 tx_uni_l; /* Tx unicast frame lower */
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u32 tx_uni_u; /* Tx unicast frame upper */
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u32 tx_multi_l; /* Tx multicast frame lower */
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u32 tx_multi_u; /* Tx multicast frame upper */
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u32 tx_brd_l; /* Tx broadcast frame lower */
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u32 tx_brd_u; /* Tx broadcast frame upper */
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u32 res_258[0x2];
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u32 tx_pkt_l; /* Tx packets lower */
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u32 tx_pkt_u; /* Tx packets upper */
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u32 tx_undsz_l; /* Tx undersized packet lower */
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u32 tx_undsz_u; /* Tx undersized packet upper */
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u32 tx_64_l; /* Tx 64 oct packet lower */
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u32 tx_64_u; /* Tx 64 oct packet upper */
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u32 tx_127_l; /* Tx 65 to 127 oct packet lower */
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u32 tx_127_u; /* Tx 65 to 127 oct packet upper */
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u32 tx_255_l; /* Tx 128 to 255 oct packet lower */
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u32 tx_255_u; /* Tx 128 to 255 oct packet upper */
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u32 tx_511_l; /* Tx 256 to 511 oct packet lower */
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u32 tx_511_u; /* Tx 256 to 511 oct packet upper */
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u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */
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u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */
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u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */
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u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */
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u32 tx_1519_l; /* Tx 1519 to max oct packet lower */
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u32 tx_1519_u; /* Tx 1519 to max oct packet upper */
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u32 res_2a8[0x6];
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u32 tx_cnp_l; /* Tx control packet lower */
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u32 tx_cnp_u; /* Tx control packet upper */
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u32 res_2c8[0xe];
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/* Line interface control register */
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u32 if_mode; /* interface mode control */
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u32 if_status; /* interface status */
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u32 res_308[0xe];
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/* HiGig/2 Register */
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u32 hg_config; /* HiGig2 control and configuration */
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u32 res_344[0x3];
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u32 hg_pause_quanta; /* HiGig2 pause quanta */
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u32 res_354[0x3];
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u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */
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u32 res_364[0x3];
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u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */
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u32 hg_fifos_status; /* HiGig2 fifos status */
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u32 rhm; /* Rx HiGig2 message counter register */
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u32 thm;/* Tx HiGig2 message counter register */
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u32 res_380[0x320];
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};
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/* COMMAND_CONFIG - command and configuration register */
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#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
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#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
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#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
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#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
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/* HASHTABLE_CTRL - Hashtable control register */
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#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
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#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
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/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
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#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
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/* IMASK - interrupt mask register */
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#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
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#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
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#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
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#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
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#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
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#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
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#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
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#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
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#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
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#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
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#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
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#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
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#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
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#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
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#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
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#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
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#define IMASK_MASK_ALL 0x00000000
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/* IEVENT - interrupt event register */
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#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
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#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
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#define IEVENT_REM_FAULT 0x00004000 /* remote fault */
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#define IEVENT_LOC_FAULT 0x00002000 /* local fault */
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#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
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#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
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#define IEVENT_TX_ER 0x00000200 /* Tx frame error */
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#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
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#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
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#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
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#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
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#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
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#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
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#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
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#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
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#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
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#define IEVENT_CLEAR_ALL 0xffffffff
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/* IF_MODE - Interface Mode Register */
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#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
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#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
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#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
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#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
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#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
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#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
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#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
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#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
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#define IF_MODE_RG 0x00000004 /* 1- RGMII */
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#define IF_MODE_RM 0x00000008 /* 1- RGMII */
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#define IF_DEFAULT (IF_GMII)
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/* Internal PHY Registers - SGMII */
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#define PHY_SGMII_CR_PHY_RESET 0x8000
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#define PHY_SGMII_CR_RESET_AN 0x0200
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#define PHY_SGMII_CR_DEF_VAL 0x1140
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#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008
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#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
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#define PHY_SGMII_IF_MODE_AN 0x0002
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#define PHY_SGMII_IF_MODE_SGMII 0x0001
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struct memac_mdio_controller {
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u32 res0[0xc];
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u32 mdio_stat; /* MDIO configuration and status */
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u32 mdio_ctl; /* MDIO control */
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u32 mdio_data; /* MDIO data */
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u32 mdio_addr; /* MDIO address */
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};
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#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
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#define MDIO_STAT_BSY (1 << 0)
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#define MDIO_STAT_RD_ER (1 << 1)
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#define MDIO_STAT_PRE (1 << 5)
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#define MDIO_STAT_ENC (1 << 6)
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#define MDIO_STAT_HOLD_15_CLK (7 << 2)
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#define MDIO_STAT_NEG (1 << 23)
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#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
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#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
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#define MDIO_CTL_PRE_DIS (1 << 10)
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#define MDIO_CTL_SCAN_EN (1 << 11)
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#define MDIO_CTL_POST_INC (1 << 14)
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#define MDIO_CTL_READ (1 << 15)
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#define MDIO_DATA(x) (x & 0xffff)
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#define MDIO_DATA_BSY (1 << 31)
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struct fsl_enet_mac;
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void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
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int max_rx_len);
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#endif
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