upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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201 lines
5.7 KiB
201 lines
5.7 KiB
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CPU_AT32AP_ATMEL_MCI_H__
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#define __CPU_AT32AP_ATMEL_MCI_H__
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/* Atmel MultiMedia Card Interface (MCI) registers */
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#define MMCI_CR 0x0000
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#define MMCI_MR 0x0004
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#define MMCI_DTOR 0x0008
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#define MMCI_SDCR 0x000c
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#define MMCI_ARGR 0x0010
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#define MMCI_CMDR 0x0014
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#define MMCI_RSPR 0x0020
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#define MMCI_RSPR1 0x0024
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#define MMCI_RSPR2 0x0028
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#define MMCI_RSPR3 0x002c
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#define MMCI_RDR 0x0030
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#define MMCI_TDR 0x0034
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#define MMCI_SR 0x0040
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#define MMCI_IER 0x0044
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#define MMCI_IDR 0x0048
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#define MMCI_IMR 0x004c
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/* Bitfields in CR */
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#define MMCI_MCIEN_OFFSET 0
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#define MMCI_MCIEN_SIZE 1
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#define MMCI_MCIDIS_OFFSET 1
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#define MMCI_MCIDIS_SIZE 1
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#define MMCI_PWSEN_OFFSET 2
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#define MMCI_PWSEN_SIZE 1
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#define MMCI_PWSDIS_OFFSET 3
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#define MMCI_PWSDIS_SIZE 1
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#define MMCI_SWRST_OFFSET 7
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#define MMCI_SWRST_SIZE 1
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/* Bitfields in MR */
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#define MMCI_CLKDIV_OFFSET 0
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#define MMCI_CLKDIV_SIZE 8
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#define MMCI_PWSDIV_OFFSET 8
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#define MMCI_PWSDIV_SIZE 3
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#define MMCI_RDPROOF_OFFSET 11
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#define MMCI_RDPROOF_SIZE 1
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#define MMCI_WRPROOF_OFFSET 12
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#define MMCI_WRPROOF_SIZE 1
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#define MMCI_PDCPADV_OFFSET 14
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#define MMCI_PDCPADV_SIZE 1
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#define MMCI_PDCMODE_OFFSET 15
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#define MMCI_PDCMODE_SIZE 1
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#define MMCI_BLKLEN_OFFSET 16
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#define MMCI_BLKLEN_SIZE 16
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/* Bitfields in DTOR */
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#define MMCI_DTOCYC_OFFSET 0
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#define MMCI_DTOCYC_SIZE 4
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#define MMCI_DTOMUL_OFFSET 4
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#define MMCI_DTOMUL_SIZE 3
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/* Bitfields in SDCR */
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#define MMCI_SCDSEL_OFFSET 0
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#define MMCI_SCDSEL_SIZE 4
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#define MMCI_SCDBUS_OFFSET 7
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#define MMCI_SCDBUS_SIZE 1
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/* Bitfields in ARGR */
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#define MMCI_ARG_OFFSET 0
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#define MMCI_ARG_SIZE 32
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/* Bitfields in CMDR */
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#define MMCI_CMDNB_OFFSET 0
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#define MMCI_CMDNB_SIZE 6
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#define MMCI_RSPTYP_OFFSET 6
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#define MMCI_RSPTYP_SIZE 2
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#define MMCI_SPCMD_OFFSET 8
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#define MMCI_SPCMD_SIZE 3
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#define MMCI_OPDCMD_OFFSET 11
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#define MMCI_OPDCMD_SIZE 1
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#define MMCI_MAXLAT_OFFSET 12
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#define MMCI_MAXLAT_SIZE 1
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#define MMCI_TRCMD_OFFSET 16
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#define MMCI_TRCMD_SIZE 2
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#define MMCI_TRDIR_OFFSET 18
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#define MMCI_TRDIR_SIZE 1
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#define MMCI_TRTYP_OFFSET 19
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#define MMCI_TRTYP_SIZE 2
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/* Bitfields in RSPRx */
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#define MMCI_RSP_OFFSET 0
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#define MMCI_RSP_SIZE 32
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/* Bitfields in SR/IER/IDR/IMR */
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#define MMCI_CMDRDY_OFFSET 0
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#define MMCI_CMDRDY_SIZE 1
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#define MMCI_RXRDY_OFFSET 1
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#define MMCI_RXRDY_SIZE 1
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#define MMCI_TXRDY_OFFSET 2
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#define MMCI_TXRDY_SIZE 1
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#define MMCI_BLKE_OFFSET 3
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#define MMCI_BLKE_SIZE 1
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#define MMCI_DTIP_OFFSET 4
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#define MMCI_DTIP_SIZE 1
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#define MMCI_NOTBUSY_OFFSET 5
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#define MMCI_NOTBUSY_SIZE 1
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#define MMCI_ENDRX_OFFSET 6
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#define MMCI_ENDRX_SIZE 1
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#define MMCI_ENDTX_OFFSET 7
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#define MMCI_ENDTX_SIZE 1
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#define MMCI_RXBUFF_OFFSET 14
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#define MMCI_RXBUFF_SIZE 1
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#define MMCI_TXBUFE_OFFSET 15
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#define MMCI_TXBUFE_SIZE 1
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#define MMCI_RINDE_OFFSET 16
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#define MMCI_RINDE_SIZE 1
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#define MMCI_RDIRE_OFFSET 17
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#define MMCI_RDIRE_SIZE 1
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#define MMCI_RCRCE_OFFSET 18
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#define MMCI_RCRCE_SIZE 1
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#define MMCI_RENDE_OFFSET 19
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#define MMCI_RENDE_SIZE 1
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#define MMCI_RTOE_OFFSET 20
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#define MMCI_RTOE_SIZE 1
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#define MMCI_DCRCE_OFFSET 21
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#define MMCI_DCRCE_SIZE 1
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#define MMCI_DTOE_OFFSET 22
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#define MMCI_DTOE_SIZE 1
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#define MMCI_OVRE_OFFSET 30
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#define MMCI_OVRE_SIZE 1
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#define MMCI_UNRE_OFFSET 31
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#define MMCI_UNRE_SIZE 1
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/* Constants for DTOMUL */
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#define MMCI_DTOMUL_1_CYCLE 0
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#define MMCI_DTOMUL_16_CYCLES 1
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#define MMCI_DTOMUL_128_CYCLES 2
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#define MMCI_DTOMUL_256_CYCLES 3
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#define MMCI_DTOMUL_1024_CYCLES 4
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#define MMCI_DTOMUL_4096_CYCLES 5
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#define MMCI_DTOMUL_65536_CYCLES 6
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#define MMCI_DTOMUL_1048576_CYCLES 7
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/* Constants for RSPTYP */
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#define MMCI_RSPTYP_NO_RESP 0
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#define MMCI_RSPTYP_48_BIT_RESP 1
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#define MMCI_RSPTYP_136_BIT_RESP 2
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/* Constants for SPCMD */
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#define MMCI_SPCMD_NO_SPEC_CMD 0
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#define MMCI_SPCMD_INIT_CMD 1
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#define MMCI_SPCMD_SYNC_CMD 2
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#define MMCI_SPCMD_INT_CMD 4
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#define MMCI_SPCMD_INT_RESP 5
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/* Constants for TRCMD */
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#define MMCI_TRCMD_NO_TRANS 0
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#define MMCI_TRCMD_START_TRANS 1
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#define MMCI_TRCMD_STOP_TRANS 2
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/* Constants for TRTYP */
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#define MMCI_TRTYP_BLOCK 0
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#define MMCI_TRTYP_MULTI_BLOCK 1
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#define MMCI_TRTYP_STREAM 2
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/* Bit manipulation macros */
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#define MMCI_BIT(name) \
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(1 << MMCI_##name##_OFFSET)
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#define MMCI_BF(name,value) \
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(((value) & ((1 << MMCI_##name##_SIZE) - 1)) \
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<< MMCI_##name##_OFFSET)
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#define MMCI_BFEXT(name,value) \
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(((value) >> MMCI_##name##_OFFSET)\
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& ((1 << MMCI_##name##_SIZE) - 1))
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#define MMCI_BFINS(name,value,old) \
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(((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \
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<< MMCI_##name##_OFFSET)) \
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| MMCI_BF(name,value))
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/* Register access macros */
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#define mmci_readl(reg) \
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readl((void *)MMCI_BASE + MMCI_##reg)
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#define mmci_writel(reg,value) \
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writel((value), (void *)MMCI_BASE + MMCI_##reg)
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#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
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