upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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552 lines
22 KiB
552 lines
22 KiB
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* t3corp.h - configuration for T3CORP (460GT)
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_460GT 1 /* Specific PPC460GT */
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#define CONFIG_440 1
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
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#endif
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#define CONFIG_HOSTNAME t3corp
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/*
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* Include common defines/options for all AMCC/APM eval boards
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*/
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#include "amcc-common.h"
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#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_FIT
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#define CFG_ALT_MEMTEST
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
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#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */
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#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */
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#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
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#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
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#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */
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/* base address of inbound PCIe window */
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#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */
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/* EBC stuff */
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
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#define CONFIG_SYS_FLASH_SIZE (64 << 20)
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#define CONFIG_SYS_FPGA1_BASE 0xe0000000
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#define CONFIG_SYS_FPGA2_BASE 0xe2000000
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#define CONFIG_SYS_FPGA3_BASE 0xe4000000
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
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#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
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#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
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#define CONFIG_SYS_FLASH_BASE_PHYS \
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(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
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| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
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#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
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#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
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#define CONFIG_SYS_SRAM_SIZE (256 << 10)
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#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
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/*
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* Initial RAM & stack pointer (placed in OCM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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/*
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* Environment
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*/
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/*
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* Define here the location of the environment variables (flash).
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*/
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#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */
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/*
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* Flash related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
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#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
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(CONFIG_SYS_FPGA1_BASE + 0x01000000) }
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#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
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0xbddf } /* set async read mode */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x4000 /* env sector size */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* DDR2 SDRAM
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*/
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#define CONFIG_SYS_MBYTES_SDRAM 256
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#define CONFIG_DDR_ECC
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#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
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#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
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#undef CONFIG_PPC4xx_DDR_METHOD_A
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#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
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/* DDR1/2 SDRAM Device Control Register Data Values */
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/* Memory Queue */
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#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \
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SDRAM_RXBAS_SDSZ_256)
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#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
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#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
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#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
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#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
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#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
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#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
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#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
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#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
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#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
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/* DDR1/2 SDRAM Device Control Register Data Values */
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#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \
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SDRAM_RXBAS_SDBE_ENABLE)
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#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
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#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \
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SDRAM_MCOPT1_PMU_OPEN | \
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SDRAM_MCOPT1_DMWD_32 | \
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SDRAM_MCOPT1_8_BANKS | \
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SDRAM_MCOPT1_DDR2_TYPE | \
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SDRAM_MCOPT1_QDEP | \
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SDRAM_MCOPT1_RWOO_DISABLED | \
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SDRAM_MCOPT1_WOOO_DISABLED | \
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SDRAM_MCOPT1_DREF_NORMAL)
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#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
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#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE
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#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
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#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
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#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
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#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
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SDRAM_CODT_DQS_1_8_V_DDR2 | \
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SDRAM_CODT_IO_NMODE)
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#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
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#define CONFIG_SYS_SDRAM0_INITPLR0 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(80) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
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#define CONFIG_SYS_SDRAM0_INITPLR1 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CONFIG_SYS_SDRAM0_INITPLR2 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
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#define CONFIG_SYS_SDRAM0_INITPLR3 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
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SDRAM_INITPLR_IMA_ENCODE(0))
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#define CONFIG_SYS_SDRAM0_INITPLR4 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \
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JEDEC_MA_EMR_RTT_150OHM))
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#define CONFIG_SYS_SDRAM0_INITPLR5 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(200) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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CAS_LATENCY | \
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JEDEC_MA_MR_BLEN_4 | \
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JEDEC_MA_MR_DLL_RESET))
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#define CONFIG_SYS_SDRAM0_INITPLR6 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(3) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
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SDRAM_INITPLR_IBA_ENCODE(0x0) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
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#define CONFIG_SYS_SDRAM0_INITPLR7 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR8 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR9 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR10 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(26) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
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#define CONFIG_SYS_SDRAM0_INITPLR11 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
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CAS_LATENCY | \
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JEDEC_MA_MR_BLEN_4))
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#define CONFIG_SYS_SDRAM0_INITPLR12 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_ENABLE | \
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JEDEC_MA_EMR_RTT_150OHM | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CONFIG_SYS_SDRAM0_INITPLR13 \
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(SDRAM_INITPLR_ENABLE | \
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SDRAM_INITPLR_IMWT_ENCODE(2) | \
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SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
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SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
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SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
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JEDEC_MA_EMR_RDQS_DISABLE | \
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JEDEC_MA_EMR_DQS_ENABLE | \
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JEDEC_MA_EMR_RTT_150OHM | \
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JEDEC_MA_EMR_ODS_NORMAL))
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#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE
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#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE
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#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
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SDRAM_RQDC_RQFD_ENCODE(56))
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#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599)
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#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
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#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
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SDRAM_DLCR_DLCS_CONT_DONE | \
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SDRAM_DLCR_DLCV_ENCODE(155))
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#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV
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#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV
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#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
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SDRAM_SDTR1_RTW_2_CLK | \
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SDRAM_SDTR1_RTRO_1_CLK)
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#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
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SDRAM_SDTR2_WTR_2_CLK | \
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SDRAM_SDTR2_XSNR_32_CLK | \
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SDRAM_SDTR2_WPC_4_CLK | \
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SDRAM_SDTR2_RPC_2_CLK | \
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SDRAM_SDTR2_RP_3_CLK | \
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SDRAM_SDTR2_RRD_2_CLK)
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#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
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SDRAM_SDTR3_RC_ENCODE(11) | \
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SDRAM_SDTR3_XCS | \
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SDRAM_SDTR3_RFC_ENCODE(26))
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#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
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CAS_LATENCY | \
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SDRAM_MMODE_BLEN_4)
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#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \
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SDRAM_MEMODE_RTT_150OHM)
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* I2C bootstrap EEPROM */
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
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/*
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* Ethernet
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*/
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_M88E1111_PHY
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/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
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#define CONFIG_M88E1111_DISABLE_FIBER
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_PHY_DYNAMIC_ANEG 1
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:RP\0" \
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"unlock=yes\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_CHIP_CONFIG
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#define CONFIG_CMD_ECCTEST
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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/*
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* PCI stuff
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI, no PCI support, only PCIe */
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#undef CONFIG_SYS_PCI_TARGET_INIT
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#undef CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/*
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* External Bus Controller (EBC) Setup
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*/
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/*
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* T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the flash has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfc00.0000 -> 4.cc00.0000
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*/
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/* Memory Bank 0 (NOR-flash) */
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#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(16) | \
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EBC_BXAP_BCE_DISABLE | \
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EBC_BXAP_BCT_2TRANS | \
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EBC_BXAP_CSN_ENCODE(1) | \
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EBC_BXAP_OEN_ENCODE(1) | \
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EBC_BXAP_WBN_ENCODE(1) | \
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EBC_BXAP_WBF_ENCODE(1) | \
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EBC_BXAP_TH_ENCODE(7) | \
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EBC_BXAP_RE_DISABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_WRITEONLY | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
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EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_16BIT)
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/* Memory Bank 1 (FPGA 1) */
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#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(5) | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(3) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(1) | \
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EBC_BXAP_RE_ENABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_RW | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
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EBC_BXCR_BS_32MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_32BIT)
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/* Memory Bank 2 (FPGA 2) */
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#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(5) | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(3) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(1) | \
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EBC_BXAP_RE_ENABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_RW | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
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EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_32BIT)
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/* Memory Bank 3 (FPGA 3) */
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#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
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EBC_BXAP_TWT_ENCODE(5) | \
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EBC_BXAP_CSN_ENCODE(0) | \
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EBC_BXAP_OEN_ENCODE(3) | \
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EBC_BXAP_WBN_ENCODE(0) | \
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EBC_BXAP_WBF_ENCODE(0) | \
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EBC_BXAP_TH_ENCODE(1) | \
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EBC_BXAP_RE_ENABLED | \
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EBC_BXAP_SOR_DELAYED | \
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EBC_BXAP_BEM_RW | \
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EBC_BXAP_PEN_DISABLED)
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#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
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EBC_BXCR_BS_16MB | \
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EBC_BXCR_BU_RW | \
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EBC_BXCR_BW_32BIT)
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/*
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* PPC4xx GPIO Configuration
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*/
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
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{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
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{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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} \
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}
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#endif /* __CONFIG_H */
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