upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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137 lines
4.9 KiB
137 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#ifndef __GDSYS_IOEP_H_
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#define __GDSYS_IOEP_H_
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/**
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* struct io_generic_packet - header structure for GDSYS IOEP packets
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* @target_address: Target protocol address of the packet.
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* @source_address: Source protocol address of the packet.
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* @packet_type: Packet type.
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* @bc: Block counter (filled in by FPGA).
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* @packet_length: Length of the packet's payload bytes.
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*/
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struct io_generic_packet {
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u16 target_address;
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u16 source_address;
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u8 packet_type;
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u8 bc;
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u16 packet_length;
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} __attribute__((__packed__));
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/**
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* struct gdsys_ioep_regs - Registers of a IOEP device
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* @transmit_data: Register that receives data to be sent
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* @tx_control: TX control register
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* @receive_data: Register filled with the received data
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* @rx_tx_status: RX/TX status register
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* @device_address: Register for setting/reading the device's address
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* @target_address: Register for setting/reading the remote endpoint's address
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* @int_enable: Interrupt/Interrupt enable register
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*/
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struct gdsys_ioep_regs {
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u16 transmit_data;
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u16 tx_control;
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u16 receive_data;
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u16 rx_tx_status;
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u16 device_address;
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u16 target_address;
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u16 int_enable;
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};
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/**
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* gdsys_ioep_set() - Convenience macro to write registers of a IOEP device
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* @map: Register map to write the value in
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* @member: Name of the member in the gdsys_ioep_regs structure to write
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* @val: Value to write to the register
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*/
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#define gdsys_ioep_set(map, member, val) \
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regmap_set(map, struct gdsys_ioep_regs, member, val)
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/**
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* gdsys_ioep_get() - Convenience macro to read registers of a IOEP device
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* @map: Register map to read the value from
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* @member: Name of the member in the gdsys_ioep_regs structure to read
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* @valp: Pointer to buffer to read the register value into
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*/
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#define gdsys_ioep_get(map, member, valp) \
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regmap_get(map, struct gdsys_ioep_regs, member, valp)
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/**
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* enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status
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* register
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* @STATE_TX_PACKET_BUILDING: The device is currently building a packet
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* (and accepting data for it)
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* @STATE_TX_TRANSMITTING: A packet is currenly being transmitted
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* @STATE_TX_BUFFER_FULL: The TX buffer is full
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* @STATE_TX_ERR: A TX error occurred
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* @STATE_RECEIVE_TIMEOUT: A receive timeout occurred
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* @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet
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* occurred
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* @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet
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* occurred
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* @STATE_RX_DIST_ERR: A error occurred in the distribution block
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* @STATE_RX_LENGTH_ERR: A length invalid error occurred
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* @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two
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* non-increasing frame count numbers
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* encountered)
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* @STATE_RX_FCS_ERR: A CRC error occurred
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* @STATE_RX_PACKET_DROPPED: A RX packet has been dropped
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* @STATE_RX_DATA_LAST: The data to be read is the final data of the
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* current packet
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* @STATE_RX_DATA_FIRST: The data to be read is the first data of the
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* current packet
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* @STATE_RX_DATA_AVAILABLE: RX data is available to be read
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*/
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enum rx_tx_status_values {
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STATE_TX_PACKET_BUILDING = BIT(0),
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STATE_TX_TRANSMITTING = BIT(1),
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STATE_TX_BUFFER_FULL = BIT(2),
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STATE_TX_ERR = BIT(3),
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STATE_RECEIVE_TIMEOUT = BIT(4),
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STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
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STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
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STATE_RX_DIST_ERR = BIT(7),
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STATE_RX_LENGTH_ERR = BIT(8),
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STATE_RX_FRAME_CTR_ERR = BIT(9),
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STATE_RX_FCS_ERR = BIT(10),
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STATE_RX_PACKET_DROPPED = BIT(11),
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STATE_RX_DATA_LAST = BIT(12),
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STATE_RX_DATA_FIRST = BIT(13),
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STATE_RX_DATA_AVAILABLE = BIT(15),
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};
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/**
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* enum tx_control_values - Enum to describe the fields of the tx_control
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* register
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* @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor
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* @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data)
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*/
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enum tx_control_values {
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CTRL_PROC_RECEIVE_ENABLE = BIT(12),
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CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
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};
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/**
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* enum int_enable_values - Enum to describe the fields of the int_enable
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* register
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* @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet
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* data can be transmitted to the
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* device)
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* @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted
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* @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received
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* @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be
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* read
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*/
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enum int_enable_values {
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IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
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IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
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IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
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IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
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};
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#endif /* __GDSYS_IOEP_H_ */
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