upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
2.6 KiB
60 lines
2.6 KiB
/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Premium & Platinum register addresses/definitions seem to be
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* identical, so we only need to use one file for both platforms.
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*/
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#ifndef _REG_FWSRAM_H_
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#define _REG_FWSRAM_H_
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#define FWSRAM_BASE 0x00030000
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/* Relative offsets of the register adresses */
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#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
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#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
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#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
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#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
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#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
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#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
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#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
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#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
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#define FWSRAM_TOP_CID1_L_OFFS 0x00002010
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#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
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#define FWSRAM_TOP_CID2_H_OFFS 0x00002014
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#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
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#define FWSRAM_TOP_CID2_L_OFFS 0x00002018
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#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
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#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
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#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
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#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
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#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
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#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
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#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
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#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
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#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
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#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
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#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
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#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
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#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
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#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
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#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
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#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
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#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
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#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
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#endif
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