upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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89 lines
2.9 KiB
89 lines
2.9 KiB
/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* Copyright (C) 2006 Micronas GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _REG_SCC_PREMIUM_H_
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#define _REG_SCC_PREMIUM_H_
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#define SCC0_BASE 0x00110000
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#define SCC1_BASE 0x00110080
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#define SCC2_BASE 0x00110100
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#define SCC3_BASE 0x00110180
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#define SCC4_BASE 0x00110200
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#define SCC5_BASE 0x00110280
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#define SCC6_BASE 0x00110300
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#define SCC7_BASE 0x00110380
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#define SCC8_BASE 0x00110400
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#define SCC9_BASE 0x00110480
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#define SCC10_BASE 0x00110500
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#define SCC11_BASE 0x00110580
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#define SCC12_BASE 0x00110600
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#define SCC13_BASE 0x00110680
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#define SCC14_BASE 0x00110700
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#define SCC15_BASE 0x00110780
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#define SCC16_BASE 0x00110800
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#define SCC17_BASE 0x00110880
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#define SCC18_BASE 0x00110900
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#define SCC19_BASE 0x00110980
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#define SCC20_BASE 0x00110a00
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#define SCC21_BASE 0x00110a80
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#define SCC22_BASE 0x00110b00
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#define SCC23_BASE 0x00110b80
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#define SCC24_BASE 0x00110c00
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#define SCC25_BASE 0x00110c80
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#define SCC26_BASE 0x00110d00
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#define SCC27_BASE 0x00110d80
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#define SCC28_BASE 0x00110e00
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#define SCC29_BASE 0x00110e80
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#define SCC30_BASE 0x00110f00
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#define SCC31_BASE 0x00110f80
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#define SCC32_BASE 0x00111000
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#define SCC33_BASE 0x00111080
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#define SCC34_BASE 0x00111100
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#define SCC35_BASE 0x00111180
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#define SCC36_BASE 0x00111200
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#define SCC37_BASE 0x00111280
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#define SCC38_BASE 0x00111300
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#define SCC39_BASE 0x00111380
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#define SCC40_BASE 0x00111400
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/* Relative offsets of the register adresses */
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#define SCC_ENABLE_OFFS 0x00000000
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#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS)
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#define SCC_RESET_OFFS 0x00000004
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#define SCC_RESET(base) ((base) + SCC_RESET_OFFS)
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#define SCC_VCID_OFFS 0x00000008
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#define SCC_VCID(base) ((base) + SCC_VCID_OFFS)
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#define SCC_MCI_CFG_OFFS 0x0000000C
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#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS)
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#define SCC_PACKET_CFG1_OFFS 0x00000010
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#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS)
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#define SCC_PACKET_CFG2_OFFS 0x00000014
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#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS)
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#define SCC_PACKET_CFG3_OFFS 0x00000018
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#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS)
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#define SCC_DMA_CFG_OFFS 0x0000001C
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#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS)
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#define SCC_CMD_OFFS 0x00000020
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#define SCC_CMD(base) ((base) + SCC_CMD_OFFS)
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#define SCC_PRIO_OFFS 0x00000024
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#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS)
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#define SCC_DEBUG_OFFS 0x00000028
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#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS)
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#define SCC_STATUS_OFFS 0x0000002C
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#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS)
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#define SCC_IMR_OFFS 0x00000030
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#define SCC_IMR(base) ((base) + SCC_IMR_OFFS)
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#define SCC_ISR_OFFS 0x00000034
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#define SCC_ISR(base) ((base) + SCC_ISR_OFFS)
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#define SCC_DMA_OFFSET_OFFS 0x00000038
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#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS)
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#define SCC_RS_CTLSTS_OFFS 0x0000003C
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#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS)
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#endif
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