upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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231 lines
11 KiB
231 lines
11 KiB
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PPC440EP_GR_H_
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#define _PPC440EP_GR_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
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#define CONFIG_NAND_NDFC
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/*
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* Some SoC specific registers (not common for all 440 SoC's)
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*/
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/* Memory mapped registers */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
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#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
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/* SDR's */
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#define SDR0_PCI0 0x0300
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#define SDR0_SDSTP2 0x4001
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#define SDR0_SDSTP3 0x4003
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#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
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#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
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#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
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#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
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#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
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#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
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#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
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#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
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#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
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#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
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#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
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#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
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#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
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Req Selection */
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#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
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#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
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#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
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Selection */
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#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
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#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
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#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
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Selection */
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#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
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Selected */
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#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
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#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
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Selection */
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#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
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Disable */
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#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
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Enable */
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#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
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Selection */
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#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
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Enable */
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#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
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Enable */
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#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
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Gated In */
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/* USB Control Register */
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#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
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#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
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#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
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#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
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#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
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#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
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/* Miscealleneaous Function Reg. */
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#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
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#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
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#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
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#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
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#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
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#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
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#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
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#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
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#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
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#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
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#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
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#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24)
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#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3)
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#define SDR0_MFR_ERRATA3_EN0 0x00800000
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#define SDR0_MFR_ERRATA3_EN1 0x00400000
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#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
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#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
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#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
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#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
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#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
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/* CUST0 Customer Configuration Register0 */
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#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
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#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
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#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
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#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
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#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
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#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
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#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
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#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
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#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
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#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
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#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
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#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24)
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#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF)
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#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
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#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22)
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#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3)
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#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
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#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
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#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
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#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
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#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
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#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
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#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
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#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4)
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#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF)
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#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
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#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
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#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
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#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
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#define SDR0_SRST_DMC 0x00200000
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#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
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#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
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#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
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#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
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#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
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#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
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#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
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#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
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#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
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#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
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#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
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#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
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#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
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#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
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#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
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#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
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#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
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#define PRADV_MASK 0x07000000 /* Primary Divisor A */
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#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
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#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
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/* Strap 1 Register */
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#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
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#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
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#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
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#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
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#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
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#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
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#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
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#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
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#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
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#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
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#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
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#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
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#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
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#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
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#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
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#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
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#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
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#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
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#define CPR0_ICFG_RLI_MASK 0x80000000
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#define CPR0_ICFG_ICS_MASK 0x00000007
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#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
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#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
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#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
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#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
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#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
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#define CPR0_PERD_PERDV0_MASK 0x07000000
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#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
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0x0EF400000 */
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/* PCI Master Local Configuration Registers */
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#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
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#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
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#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
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#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
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#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
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#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
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#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
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#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
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#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
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#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
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#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
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#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
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/* PCI Target Local Configuration Registers */
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#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
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Attribute */
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#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
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#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
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Attribute */
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#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
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#endif /* _PPC440EP_GR_H_ */
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