upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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538 lines
14 KiB
538 lines
14 KiB
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/processor.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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#include <net.h>
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#include <asm/fec.h>
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#endif
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void init_fbcs(void)
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{
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fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
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#if !defined(CONFIG_SERIAL_BOOT)
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
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out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
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out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
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out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
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#endif
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
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/* Latch chipselect */
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out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
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out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
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out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
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out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
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out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
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out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
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out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
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out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
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out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
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out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
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out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
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out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
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out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
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out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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}
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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#ifdef CONFIG_MCF5441x
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scm_t *scm = (scm_t *) MMAP_SCM;
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pm_t *pm = (pm_t *) MMAP_PM;
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/* Disable Switch */
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*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
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/* Disable core watchdog */
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out_be16(&scm->cwcr, 0);
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out_8(&gpio->par_fbctl,
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GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
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GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
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GPIO_PAR_FBCTL_TA_TA);
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out_8(&gpio->par_be,
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GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
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GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
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/* eDMA */
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out_8(&pm->pmcr0, 17);
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/* INTR0 - INTR2 */
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out_8(&pm->pmcr0, 18);
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out_8(&pm->pmcr0, 19);
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out_8(&pm->pmcr0, 20);
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/* I2C */
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out_8(&pm->pmcr0, 22);
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out_8(&pm->pmcr1, 4);
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out_8(&pm->pmcr1, 7);
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/* DTMR0 - DTMR3*/
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out_8(&pm->pmcr0, 28);
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out_8(&pm->pmcr0, 29);
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out_8(&pm->pmcr0, 30);
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out_8(&pm->pmcr0, 31);
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/* PIT0 - PIT3 */
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out_8(&pm->pmcr0, 32);
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out_8(&pm->pmcr0, 33);
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out_8(&pm->pmcr0, 34);
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out_8(&pm->pmcr0, 35);
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/* Edge Port */
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out_8(&pm->pmcr0, 36);
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out_8(&pm->pmcr0, 37);
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/* USB OTG */
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out_8(&pm->pmcr0, 44);
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/* USB Host */
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out_8(&pm->pmcr0, 45);
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/* ESDHC */
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out_8(&pm->pmcr0, 51);
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/* ENET0 - ENET1 */
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out_8(&pm->pmcr0, 53);
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out_8(&pm->pmcr0, 54);
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/* NAND */
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out_8(&pm->pmcr0, 63);
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#ifdef CONFIG_SYS_I2C_0
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out_8(&gpio->par_cani2c, 0xF0);
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/* I2C0 pull up */
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out_be16(&gpio->pcr_b, 0x003C);
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/* I2C0 max speed */
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out_8(&gpio->srcr_cani2c, 0x03);
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#endif
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#ifdef CONFIG_SYS_I2C_2
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/* I2C2 */
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out_8(&gpio->par_ssi0h, 0xA0);
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/* I2C2, UART7 */
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out_8(&gpio->par_ssi0h, 0xA8);
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/* UART7 */
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out_8(&gpio->par_ssi0l, 0x2);
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/* UART8, UART9 */
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out_8(&gpio->par_cani2c, 0xAA);
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/* UART4, UART0 */
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out_8(&gpio->par_uart0, 0xAF);
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/* UART5, UART1 */
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out_8(&gpio->par_uart1, 0xAF);
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/* UART6, UART2 */
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out_8(&gpio->par_uart2, 0xAF);
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/* I2C2 pull up */
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out_be16(&gpio->pcr_h, 0xF000);
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#endif
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#ifdef CONFIG_SYS_I2C_5
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/* I2C5 */
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out_8(&gpio->par_uart1, 0x0A);
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/* I2C5 pull up */
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out_be16(&gpio->pcr_e, 0x0003);
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out_be16(&gpio->pcr_f, 0xC000);
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#endif
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/* Lowest slew rate for UART0,1,2 */
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out_8(&gpio->srcr_uart, 0x00);
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#endif /* CONFIG_MCF5441x */
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#ifdef CONFIG_MCF5445x
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scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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out_be32(&scm1->mpr, 0x77777777);
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out_be32(&scm1->pacra, 0);
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out_be32(&scm1->pacrb, 0);
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out_be32(&scm1->pacrc, 0);
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out_be32(&scm1->pacrd, 0);
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out_be32(&scm1->pacre, 0);
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out_be32(&scm1->pacrf, 0);
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out_be32(&scm1->pacrg, 0);
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/* FlexBus */
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out_8(&gpio->par_be,
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GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
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GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
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out_8(&gpio->par_fbctl,
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GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
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GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
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#ifdef CONFIG_SYS_FSL_I2C
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out_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
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#endif
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#endif /* CONFIG_MCF5445x */
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/* FlexBus Chipselect */
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init_fbcs();
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#ifdef CONFIG_SYS_CS0_BASE
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/*
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* now the flash base address is no longer at 0 (Newer ColdFire family
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* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
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* also move to the new location.
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*/
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if (CONFIG_SYS_CS0_BASE != 0)
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setvbr(CONFIG_SYS_CS0_BASE);
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFRTC
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rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
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rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
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out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
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out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
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#endif
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return (0);
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}
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void uart_port_conf(int port)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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#ifdef CONFIG_MCF5441x
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pm_t *pm = (pm_t *) MMAP_PM;
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#endif
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/* Setup Ports: */
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switch (port) {
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#ifdef CONFIG_MCF5441x
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case 0:
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/* UART0 */
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out_8(&pm->pmcr0, 24);
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clrbits_8(&gpio->par_uart0,
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~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
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setbits_8(&gpio->par_uart0,
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GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
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break;
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case 1:
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/* UART1 */
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out_8(&pm->pmcr0, 25);
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clrbits_8(&gpio->par_uart1,
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~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
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setbits_8(&gpio->par_uart1,
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GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
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break;
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case 2:
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/* UART2 */
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out_8(&pm->pmcr0, 26);
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clrbits_8(&gpio->par_uart2,
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~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
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setbits_8(&gpio->par_uart2,
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GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
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break;
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case 3:
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/* UART3 */
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out_8(&pm->pmcr0, 27);
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clrbits_8(&gpio->par_dspi0,
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~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
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setbits_8(&gpio->par_dspi0,
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GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
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break;
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case 4:
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/* UART4 */
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out_8(&pm->pmcr1, 24);
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clrbits_8(&gpio->par_uart0,
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~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
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setbits_8(&gpio->par_uart0,
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GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
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break;
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case 5:
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/* UART5 */
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out_8(&pm->pmcr1, 25);
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clrbits_8(&gpio->par_uart1,
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~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
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setbits_8(&gpio->par_uart1,
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GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
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break;
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case 6:
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/* UART6 */
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out_8(&pm->pmcr1, 26);
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clrbits_8(&gpio->par_uart2,
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~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
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setbits_8(&gpio->par_uart2,
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GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
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break;
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case 7:
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/* UART7 */
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out_8(&pm->pmcr1, 27);
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clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
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clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
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setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
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setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
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break;
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case 8:
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/* UART8 */
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out_8(&pm->pmcr0, 28);
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clrbits_8(&gpio->par_cani2c,
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~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
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setbits_8(&gpio->par_cani2c,
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GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
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break;
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case 9:
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/* UART9 */
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out_8(&pm->pmcr1, 29);
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clrbits_8(&gpio->par_cani2c,
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~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
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setbits_8(&gpio->par_cani2c,
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GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
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break;
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#endif
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#ifdef CONFIG_MCF5445x
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case 0:
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clrbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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setbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
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break;
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case 1:
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#ifdef CONFIG_SYS_UART1_PRI_GPIO
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clrbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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setbits_8(&gpio->par_uart,
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GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
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#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
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clrbits_be16(&gpio->par_ssi,
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~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
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setbits_be16(&gpio->par_ssi,
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GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
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#endif
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break;
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case 2:
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#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
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clrbits_8(&gpio->par_timer,
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~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
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setbits_8(&gpio->par_timer,
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GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
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#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
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clrbits_8(&gpio->par_timer,
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~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
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setbits_8(&gpio->par_timer,
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GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
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#endif
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break;
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#endif /* CONFIG_MCF5445x */
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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#ifdef CONFIG_MCF5445x
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struct fec_info_s *info = (struct fec_info_s *)dev->priv;
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if (setclear) {
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#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 |
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GPIO_PAR_FECI2C_MDIO0_MDIO0);
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else
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC1_MDC1 |
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GPIO_PAR_FECI2C_MDIO1_MDIO1);
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#else
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setbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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#endif
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
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else
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
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} else {
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clrbits_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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#ifdef CONFIG_SYS_FEC_FULL_MII
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
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#else
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clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
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#endif
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} else {
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#ifdef CONFIG_SYS_FEC_FULL_MII
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setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
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#else
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clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
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#endif
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}
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}
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#endif /* CONFIG_MCF5445x */
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#ifdef CONFIG_MCF5441x
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if (setclear) {
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out_8(&gpio->par_fec, 0x03);
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out_8(&gpio->srcr_fec, 0x0F);
|
|
clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
|
|
GPIO_PAR_SIMP0H_DAT_GPIO);
|
|
clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
|
|
GPIO_PDDR_G4_OUTPUT);
|
|
clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
|
|
|
|
} else
|
|
clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CF_DSPI
|
|
void cfspi_port_conf(void)
|
|
{
|
|
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
|
|
|
#ifdef CONFIG_MCF5445x
|
|
out_8(&gpio->par_dspi,
|
|
GPIO_PAR_DSPI_SIN_SIN |
|
|
GPIO_PAR_DSPI_SOUT_SOUT |
|
|
GPIO_PAR_DSPI_SCK_SCK);
|
|
#endif
|
|
|
|
#ifdef CONFIG_MCF5441x
|
|
pm_t *pm = (pm_t *) MMAP_PM;
|
|
|
|
out_8(&gpio->par_dspi0,
|
|
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
|
|
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
|
|
out_8(&gpio->srcr_dspiow, 3);
|
|
|
|
/* DSPI0 */
|
|
out_8(&pm->pmcr0, 23);
|
|
#endif
|
|
}
|
|
|
|
int cfspi_claim_bus(uint bus, uint cs)
|
|
{
|
|
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
|
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
|
|
|
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
|
|
return -1;
|
|
|
|
/* Clear FIFO and resume transfer */
|
|
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
|
|
|
|
#ifdef CONFIG_MCF5445x
|
|
switch (cs) {
|
|
case 0:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
|
|
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
|
|
break;
|
|
case 1:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
|
|
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
|
|
break;
|
|
case 2:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
|
|
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
|
|
break;
|
|
case 3:
|
|
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
|
|
setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
|
|
break;
|
|
case 5:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
|
|
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MCF5441x
|
|
switch (cs) {
|
|
case 0:
|
|
clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
|
|
setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
|
|
break;
|
|
case 1:
|
|
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
|
|
setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cfspi_release_bus(uint bus, uint cs)
|
|
{
|
|
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
|
|
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
|
|
|
|
/* Clear FIFO */
|
|
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
|
|
|
|
#ifdef CONFIG_MCF5445x
|
|
switch (cs) {
|
|
case 0:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
|
|
break;
|
|
case 1:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
|
|
break;
|
|
case 2:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
|
|
break;
|
|
case 3:
|
|
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
|
|
break;
|
|
case 5:
|
|
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MCF5441x
|
|
if (cs == 1)
|
|
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
|
|
#endif
|
|
}
|
|
#endif
|
|
|