upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
3.0 KiB
118 lines
3.0 KiB
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ETH_PHY_CTRL_REG 0
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
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* "RD-AXP-GP rev 1.0".
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*
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* GPPs
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* MPP# NAME IN/OUT
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* ----------------------------------------------
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* 21 SW_Reset_ OUT
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* 25 Phy_Int# IN
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* 28 SDI_WP IN
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* 29 SDI_Status IN
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* 54-61 On GPP Connector ?
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* 62 Switch Interrupt IN
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* 63-65 Reserved from SW Board ?
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* 66 SW_BRD connected IN
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*/
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#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
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#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
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#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
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#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
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#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
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#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x00000000, MVEBU_MPP_BASE + 0x00);
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writel(0x00000000, MVEBU_MPP_BASE + 0x04);
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writel(0x33000000, MVEBU_MPP_BASE + 0x08);
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writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
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writel(0x11111111, MVEBU_MPP_BASE + 0x10);
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writel(0x00221100, MVEBU_MPP_BASE + 0x14);
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writel(0x00000003, MVEBU_MPP_BASE + 0x18);
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writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
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writel(0x00000000, MVEBU_MPP_BASE + 0x20);
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/* Configure GPIO */
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writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
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writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Marvell DB-MV784MP-GP\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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u16 reg;
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/* Enable QSGMII AN */
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/* Set page to 4 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
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/* Enable AN */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
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/* Set page to 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
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/* Phy C_ANEG */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
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reg |= 0x1E0;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
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/* Soft-Reset */
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phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
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/* Power up the phy */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
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reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
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phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
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printf("88E1545 Initialized\n");
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return 0;
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}
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