upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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385 lines
9.6 KiB
385 lines
9.6 KiB
/*
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* NVIDIA Tegra20 GPIO handling.
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* (C) Copyright 2010-2012,2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
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* Tom Warren (twarren@nvidia.com)
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include <asm/arch/tegra.h>
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#include <asm/gpio.h>
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const int CONFIG_SFIO = 0;
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static const int CONFIG_GPIO = 1;
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static const int DIRECTION_INPUT = 0;
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static const int DIRECTION_OUTPUT = 1;
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struct tegra_gpio_platdata {
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struct gpio_ctlr_bank *bank;
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const char *port_name; /* Name of port, e.g. "B" */
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int base_gpio; /* Port number for this port (0, 1,.., n-1) */
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};
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/* Information about each port at run-time */
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struct tegra_port_info {
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struct gpio_ctlr_bank *bank;
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int base_gpio; /* Port number for this port (0, 1,.., n-1) */
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};
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/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
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static int get_config(unsigned gpio)
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{
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struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
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u32 u;
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int type;
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u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
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type = (u >> GPIO_BIT(gpio)) & 1;
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debug("get_config: port = %d, bit = %d is %s\n",
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GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
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return type ? CONFIG_GPIO : CONFIG_SFIO;
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}
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/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
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static void set_config(unsigned gpio, int type)
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{
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struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
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u32 u;
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debug("set_config: port = %d, bit = %d, %s\n",
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GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
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u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
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if (type != CONFIG_SFIO)
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u |= 1 << GPIO_BIT(gpio);
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else
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u &= ~(1 << GPIO_BIT(gpio));
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writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
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}
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/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
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static int get_direction(unsigned gpio)
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{
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struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
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u32 u;
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int dir;
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u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
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dir = (u >> GPIO_BIT(gpio)) & 1;
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debug("get_direction: port = %d, bit = %d, %s\n",
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GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
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return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
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}
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/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
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static void set_direction(unsigned gpio, int output)
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{
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struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
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u32 u;
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debug("set_direction: port = %d, bit = %d, %s\n",
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GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
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u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
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if (output != DIRECTION_INPUT)
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u |= 1 << GPIO_BIT(gpio);
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else
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u &= ~(1 << GPIO_BIT(gpio));
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writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
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}
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/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
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static void set_level(unsigned gpio, int high)
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{
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struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
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u32 u;
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debug("set_level: port = %d, bit %d == %d\n",
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GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
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u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
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if (high)
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u |= 1 << GPIO_BIT(gpio);
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else
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u &= ~(1 << GPIO_BIT(gpio));
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writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
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}
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/*
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* Generic_GPIO primitives.
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*/
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/* set GPIO pin 'gpio' as an input */
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static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct tegra_port_info *state = dev_get_priv(dev);
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/* Configure GPIO direction as input. */
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set_direction(state->base_gpio + offset, DIRECTION_INPUT);
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/* Enable the pin as a GPIO */
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set_config(state->base_gpio + offset, 1);
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return 0;
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}
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/* set GPIO pin 'gpio' as an output, with polarity 'value' */
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static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct tegra_port_info *state = dev_get_priv(dev);
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int gpio = state->base_gpio + offset;
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/* Configure GPIO output value. */
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set_level(gpio, value);
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/* Configure GPIO direction as output. */
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set_direction(gpio, DIRECTION_OUTPUT);
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/* Enable the pin as a GPIO */
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set_config(state->base_gpio + offset, 1);
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return 0;
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}
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/* read GPIO IN value of pin 'gpio' */
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static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct tegra_port_info *state = dev_get_priv(dev);
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int gpio = state->base_gpio + offset;
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int val;
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debug("%s: pin = %d (port %d:bit %d)\n", __func__,
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gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
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if (get_direction(gpio) == DIRECTION_INPUT)
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val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
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else
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val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
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return (val >> GPIO_BIT(gpio)) & 1;
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}
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/* write GPIO OUT value to pin 'gpio' */
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static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
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{
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struct tegra_port_info *state = dev_get_priv(dev);
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int gpio = state->base_gpio + offset;
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debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
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gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
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/* Configure GPIO output value. */
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set_level(gpio, value);
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return 0;
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}
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void gpio_config_table(const struct tegra_gpio_config *config, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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switch (config[i].init) {
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case TEGRA_GPIO_INIT_IN:
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set_direction(config[i].gpio, DIRECTION_INPUT);
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break;
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case TEGRA_GPIO_INIT_OUT0:
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set_level(config[i].gpio, 0);
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set_direction(config[i].gpio, DIRECTION_OUTPUT);
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break;
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case TEGRA_GPIO_INIT_OUT1:
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set_level(config[i].gpio, 1);
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set_direction(config[i].gpio, DIRECTION_OUTPUT);
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break;
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}
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set_config(config[i].gpio, CONFIG_GPIO);
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}
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}
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static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct tegra_port_info *state = dev_get_priv(dev);
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int gpio = state->base_gpio + offset;
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if (!get_config(gpio))
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return GPIOF_FUNC;
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else if (get_direction(gpio))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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int gpio, port, ret;
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gpio = args->args[0];
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port = gpio / TEGRA_GPIOS_PER_PORT;
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ret = device_get_child(dev, port, &desc->dev);
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if (ret)
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return ret;
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desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops gpio_tegra_ops = {
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.direction_input = tegra_gpio_direction_input,
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.direction_output = tegra_gpio_direction_output,
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.get_value = tegra_gpio_get_value,
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.set_value = tegra_gpio_set_value,
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.get_function = tegra_gpio_get_function,
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.xlate = tegra_gpio_xlate,
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};
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/**
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* Returns the name of a GPIO port
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*
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* GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
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*
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* @base_port: Base port number (0, 1..n-1)
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* @return allocated string containing the name
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*/
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static char *gpio_port_name(int base_port)
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{
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char *name, *s;
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name = malloc(3);
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if (name) {
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s = name;
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*s++ = 'A' + (base_port % 26);
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if (base_port >= 26)
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*s++ = *name;
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*s = '\0';
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}
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return name;
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}
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static const struct udevice_id tegra_gpio_ids[] = {
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{ .compatible = "nvidia,tegra30-gpio" },
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{ .compatible = "nvidia,tegra20-gpio" },
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{ }
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};
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static int gpio_tegra_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct tegra_port_info *priv = dev->priv;
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struct tegra_gpio_platdata *plat = dev->platdata;
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/* Only child devices have ports */
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if (!plat)
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return 0;
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priv->bank = plat->bank;
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priv->base_gpio = plat->base_gpio;
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uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
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uc_priv->bank_name = plat->port_name;
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return 0;
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}
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/**
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* We have a top-level GPIO device with no actual GPIOs. It has a child
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* device for each Tegra port.
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*/
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static int gpio_tegra_bind(struct udevice *parent)
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{
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struct tegra_gpio_platdata *plat = parent->platdata;
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struct gpio_ctlr *ctlr;
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int bank_count;
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int bank;
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int ret;
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/* If this is a child device, there is nothing to do here */
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if (plat)
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return 0;
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/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
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#ifdef CONFIG_SPL_BUILD
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ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
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bank_count = TEGRA_GPIO_BANKS;
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#else
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{
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int len;
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/*
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* This driver does not make use of interrupts, other than to figure
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* out the number of GPIO banks
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*/
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len = dev_read_size(parent, "interrupts");
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if (len < 0)
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return len;
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bank_count = len / 3 / sizeof(u32);
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ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
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if ((ulong)ctlr == FDT_ADDR_T_NONE)
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return -EINVAL;
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}
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#endif
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for (bank = 0; bank < bank_count; bank++) {
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int port;
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for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
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struct tegra_gpio_platdata *plat;
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struct udevice *dev;
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int base_port;
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plat = calloc(1, sizeof(*plat));
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if (!plat)
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return -ENOMEM;
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plat->bank = &ctlr->gpio_bank[bank];
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base_port = bank * TEGRA_PORTS_PER_BANK + port;
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plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
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plat->port_name = gpio_port_name(base_port);
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ret = device_bind(parent, parent->driver,
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plat->port_name, plat, -1, &dev);
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if (ret)
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return ret;
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dev_set_of_offset(dev, dev_of_offset(parent));
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}
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}
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return 0;
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}
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U_BOOT_DRIVER(gpio_tegra) = {
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.name = "gpio_tegra",
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.id = UCLASS_GPIO,
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.of_match = tegra_gpio_ids,
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.bind = gpio_tegra_bind,
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.probe = gpio_tegra_probe,
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.priv_auto_alloc_size = sizeof(struct tegra_port_info),
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.ops = &gpio_tegra_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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