upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
3.9 KiB
113 lines
3.9 KiB
/*
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* Support for indirect PCI bridges.
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*
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* Copyright (C) 1998 Gabriel Paubert.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#ifndef __I386__
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#define cfg_read(val, addr, type, op) *val = op((type)(addr))
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
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#if defined(CONFIG_MPC8260)
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
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sync(); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#elif defined(CONFIG_E500)
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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*(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
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sync(); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#elif defined(CONFIG_440_GX)
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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if (PCI_BUS(dev) > 0) \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
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else \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#else
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#endif
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#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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unsigned int msr = mfmsr(); \
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mtmsr(msr & ~(MSR_EE | MSR_CE)); \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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out_le32(hose->cfg_addr, 0x00000000); \
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mtmsr(msr); \
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return 0; \
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}
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INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
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INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
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INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
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#ifdef CONFIG_405GP
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INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
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INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
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INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
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#else
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INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
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INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
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INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
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#endif
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void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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{
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pci_set_ops(hose,
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indirect_read_config_byte,
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indirect_read_config_word,
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indirect_read_config_dword,
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indirect_write_config_byte,
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indirect_write_config_word,
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indirect_write_config_dword);
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hose->cfg_addr = (unsigned int *) cfg_addr;
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hose->cfg_data = (unsigned char *) cfg_data;
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}
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#endif
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#endif
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