upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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65 lines
1.7 KiB
65 lines
1.7 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x0] = {PCIE1, NONE, NONE, NONE},
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[0x2] = {PCIE1, PCIE2, PCIE3, PCIE3},
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[0x4] = {PCIE1, PCIE1, PCIE3, PCIE3},
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[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0x7] = {SRIO2, SRIO1, NONE, NONE},
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[0x8] = {SRIO2, SRIO2, SRIO2, SRIO2},
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[0x9] = {SRIO2, SRIO2, SRIO2, SRIO2},
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[0xa] = {SRIO2, SRIO2, SRIO2, SRIO2},
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[0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
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[0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
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[0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
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[0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
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[0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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if (!(serdes1_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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if (serdes1_prtcl_map & (1 << NONE))
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return;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes1_prtcl_map |= (1 << NONE);
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}
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