upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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67 lines
2.3 KiB
67 lines
2.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
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PCIE2, PCIE2, PCIE2, PCIE2},
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[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
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PCIE2, PCIE3, PCIE4, SATA1},
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[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
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PCIE2, PCIE3, SATA2, SATA1},
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[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE2, PCIE2, PCIE2},
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[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
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PCIE2, PCIE2, PCIE2, PCIE2},
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[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
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PCIE2, PCIE3, PCIE4, SATA1},
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[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
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PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
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[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
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PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
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[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE3, PCIE4, SATA1},
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[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
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[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
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PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
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[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
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PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
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[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
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[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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