upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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109 lines
1.8 KiB
109 lines
1.8 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
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* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define CACHE_VALID 1
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#define CACHE_UPDATED 2
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static inline void cache_wback_all(void)
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{
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unsigned long addr, data, i, j;
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for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
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for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
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addr = CACHE_OC_ADDRESS_ARRAY
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| (j << CACHE_OC_WAY_SHIFT)
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| (i << CACHE_OC_ENTRY_SHIFT);
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data = inl(addr);
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if (data & CACHE_UPDATED) {
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data &= ~CACHE_UPDATED;
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outl(data, addr);
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}
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}
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}
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}
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#define CACHE_ENABLE 0
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#define CACHE_DISABLE 1
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static int cache_control(unsigned int cmd)
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{
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unsigned long ccr;
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jump_to_P2();
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ccr = inl(CCR);
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if (ccr & CCR_CACHE_ENABLE)
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cache_wback_all();
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if (cmd == CACHE_DISABLE)
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outl(CCR_CACHE_STOP, CCR);
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else
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outl(CCR_CACHE_INIT, CCR);
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back_to_P1();
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return 0;
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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u32 v;
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile ("ocbp %0" : /* no output */
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: "m" (__m(v)));
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}
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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u32 v;
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile ("ocbi %0" : /* no output */
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: "m" (__m(v)));
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr , addr + size);
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}
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void icache_enable(void)
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{
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cache_control(CACHE_ENABLE);
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}
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void icache_disable(void)
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{
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cache_control(CACHE_DISABLE);
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}
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int icache_status(void)
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{
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return 0;
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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