upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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412 lines
9.6 KiB
412 lines
9.6 KiB
/*
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* linux/arch/ppc/kernel/traps.c
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modified by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras (paulus@cs.anu.edu.au)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This file handles the architecture-dependent parts of hardware exceptions
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_KGDB)
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int (*debugger_exception_handler)(struct pt_regs *) = 0;
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#endif
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/* Returns 0 if exception not found and fixup otherwise. */
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extern unsigned long search_exception_table(unsigned long);
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/* THIS NEEDS CHANGING to use the board info structure.
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*/
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#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
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static __inline__ void set_tsr(unsigned long val)
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{
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#if defined(CONFIG_440)
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asm volatile("mtspr 0x150, %0" : : "r" (val));
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#else
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asm volatile("mttsr %0" : : "r" (val));
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#endif
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}
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static __inline__ unsigned long get_esr(void)
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{
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unsigned long val;
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#if defined(CONFIG_440)
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asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
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#else
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asm volatile("mfesr %0" : "=r" (val) :);
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#endif
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return val;
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}
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#define ESR_MCI 0x80000000
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#define ESR_PIL 0x08000000
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#define ESR_PPR 0x04000000
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#define ESR_PTR 0x02000000
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#define ESR_DST 0x00800000
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#define ESR_DIZ 0x00400000
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#define ESR_U0F 0x00008000
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#if defined(CONFIG_CMD_BEDBUG)
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extern void do_bedbug_breakpoint(struct pt_regs *);
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#endif
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/*
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* Trap & Exception support
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*/
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void
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print_backtrace(unsigned long *sp)
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{
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int cnt = 0;
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unsigned long i;
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printf("Call backtrace: ");
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while (sp) {
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if ((uint)sp > END_OF_MEM)
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break;
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i = sp[1];
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if (cnt++ % 7 == 0)
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printf("\n");
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printf("%08lX ", i);
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if (cnt > 32) break;
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sp = (unsigned long *)*sp;
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}
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printf("\n");
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}
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void show_regs(struct pt_regs * regs)
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{
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int i;
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printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
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regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
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printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
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regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
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regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
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regs->msr&MSR_IR ? 1 : 0,
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regs->msr&MSR_DR ? 1 : 0);
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printf("\n");
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for (i = 0; i < 32; i++) {
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if ((i % 8) == 0) {
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printf("GPR%02d: ", i);
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}
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printf("%08lX ", regs->gpr[i]);
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if ((i % 8) == 7) {
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printf("\n");
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}
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}
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}
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void
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_exception(int signr, struct pt_regs *regs)
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{
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show_regs(regs);
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print_backtrace((unsigned long *)regs->gpr[1]);
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panic("Exception");
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}
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void
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MachineCheckException(struct pt_regs *regs)
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{
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unsigned long fixup, val;
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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u32 value2;
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int corr_ecc = 0;
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int uncorr_ecc = 0;
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#endif
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if ((fixup = search_exception_table(regs->nip)) != 0) {
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regs->nip = fixup;
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val = mfspr(MCSR);
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/* Clear MCSR */
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mtspr(SPRN_MCSR, val);
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return;
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}
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#if defined(CONFIG_CMD_KGDB)
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if (debugger_exception_handler && (*debugger_exception_handler)(regs))
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return;
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#endif
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printf("Machine Check Exception.\n");
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printf("Caused by (from msr): ");
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printf("regs %p ", regs);
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val = get_esr();
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#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
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if (val& ESR_IMCP) {
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printf("Instruction");
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mtspr(ESR, val & ~ESR_IMCP);
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} else {
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printf("Data");
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}
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printf(" machine check.\n");
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#elif defined(CONFIG_440) || defined(CONFIG_405EX)
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if (val& ESR_IMCP){
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printf("Instruction Synchronous Machine Check exception\n");
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mtspr(SPRN_ESR, val & ~ESR_IMCP);
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} else {
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val = mfspr(MCSR);
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if (val & MCSR_IB)
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printf("Instruction Read PLB Error\n");
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#if defined(CONFIG_440)
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if (val & MCSR_DRB)
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printf("Data Read PLB Error\n");
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if (val & MCSR_DWB)
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printf("Data Write PLB Error\n");
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#else
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if (val & MCSR_DB)
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printf("Data PLB Error\n");
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#endif
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if (val & MCSR_TLBP)
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printf("TLB Parity Error\n");
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if (val & MCSR_ICP){
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/*flush_instruction_cache(); */
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printf("I-Cache Parity Error\n");
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}
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if (val & MCSR_DCSP)
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printf("D-Cache Search Parity Error\n");
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if (val & MCSR_DCFP)
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printf("D-Cache Flush Parity Error\n");
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if (val & MCSR_IMPE)
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printf("Machine Check exception is imprecise\n");
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/* Clear MCSR */
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mtspr(SPRN_MCSR, val);
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}
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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mfsdram(DDR0_00, val) ;
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printf("DDR0: DDR0_00 %lx\n", val);
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val = (val >> 16) & 0xff;
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if (val & 0x80)
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printf("DDR0: At least one interrupt active\n");
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if (val & 0x40)
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printf("DDR0: DRAM initialization complete.\n");
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if (val & 0x20) {
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printf("DDR0: Multiple uncorrectable ECC events.\n");
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uncorr_ecc = 1;
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}
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if (val & 0x10) {
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printf("DDR0: Single uncorrectable ECC event.\n");
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uncorr_ecc = 1;
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}
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if (val & 0x08) {
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printf("DDR0: Multiple correctable ECC events.\n");
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corr_ecc = 1;
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}
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if (val & 0x04) {
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printf("DDR0: Single correctable ECC event.\n");
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corr_ecc = 1;
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}
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if (val & 0x02)
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printf("Multiple accesses outside the defined"
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" physical memory space detected\n");
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if (val & 0x01)
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printf("DDR0: Single access outside the defined"
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" physical memory space detected.\n");
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mfsdram(DDR0_01, val);
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val = (val >> 8) & 0x7;
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switch (val ) {
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case 0:
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printf("DDR0: Write Out-of-Range command\n");
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break;
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case 1:
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printf("DDR0: Read Out-of-Range command\n");
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break;
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case 2:
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printf("DDR0: Masked write Out-of-Range command\n");
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break;
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case 4:
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printf("DDR0: Wrap write Out-of-Range command\n");
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break;
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case 5:
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printf("DDR0: Wrap read Out-of-Range command\n");
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break;
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default:
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mfsdram(DDR0_01, value2);
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printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
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}
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mfsdram(DDR0_23, val);
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if (((val >> 16) & 0xff) && corr_ecc)
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printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
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(val >> 16) & 0xff);
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mfsdram(DDR0_23, val);
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if (((val >> 8) & 0xff) && uncorr_ecc)
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printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
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(val >> 8) & 0xff);
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mfsdram(DDR0_33, val);
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if (val)
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printf("DDR0: Address of command that caused an "
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"Out-of-Range interrupt %lx\n", val);
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mfsdram(DDR0_34, val);
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if (val && uncorr_ecc)
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printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
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mfsdram(DDR0_35, val);
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if (val && uncorr_ecc)
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printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
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mfsdram(DDR0_36, val);
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if (val && uncorr_ecc)
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printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
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mfsdram(DDR0_37, val);
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if (val && uncorr_ecc)
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printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
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mfsdram(DDR0_38, val);
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if (val && corr_ecc)
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printf("DDR0: Address of correctable ECC event %lx\n", val);
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mfsdram(DDR0_39, val);
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if (val && corr_ecc)
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printf("DDR0: Address of correctable ECC event %lx\n", val);
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mfsdram(DDR0_40, val);
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if (val && corr_ecc)
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printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
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mfsdram(DDR0_41, val);
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if (val && corr_ecc)
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printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
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#endif /* CONFIG_440EPX */
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#endif /* CONFIG_440 */
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show_regs(regs);
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print_backtrace((unsigned long *)regs->gpr[1]);
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panic("machine check");
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}
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void
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AlignmentException(struct pt_regs *regs)
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{
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#if defined(CONFIG_CMD_KGDB)
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if (debugger_exception_handler && (*debugger_exception_handler)(regs))
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return;
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#endif
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show_regs(regs);
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print_backtrace((unsigned long *)regs->gpr[1]);
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panic("Alignment Exception");
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}
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void
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ProgramCheckException(struct pt_regs *regs)
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{
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long esr_val;
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#if defined(CONFIG_CMD_KGDB)
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if (debugger_exception_handler && (*debugger_exception_handler)(regs))
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return;
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#endif
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show_regs(regs);
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esr_val = get_esr();
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if( esr_val & ESR_PIL )
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printf( "** Illegal Instruction **\n" );
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else if( esr_val & ESR_PPR )
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printf( "** Privileged Instruction **\n" );
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else if( esr_val & ESR_PTR )
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printf( "** Trap Instruction **\n" );
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print_backtrace((unsigned long *)regs->gpr[1]);
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panic("Program Check Exception");
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}
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void
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DecrementerPITException(struct pt_regs *regs)
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{
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/*
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* Reset PIT interrupt
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*/
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set_tsr(0x08000000);
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/*
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* Call timer_interrupt routine in interrupts.c
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*/
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timer_interrupt(NULL);
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}
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void
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UnknownException(struct pt_regs *regs)
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{
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#if defined(CONFIG_CMD_KGDB)
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if (debugger_exception_handler && (*debugger_exception_handler)(regs))
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return;
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#endif
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printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
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regs->nip, regs->msr, regs->trap);
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_exception(0, regs);
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}
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void
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DebugException(struct pt_regs *regs)
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{
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printf("Debugger trap at @ %lx\n", regs->nip );
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show_regs(regs);
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#if defined(CONFIG_CMD_BEDBUG)
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do_bedbug_breakpoint( regs );
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#endif
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}
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/* Probe an address by reading. If not present, return -1, otherwise
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* return 0.
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*/
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int
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addr_probe(uint *addr)
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{
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#if 0
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int retval;
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__asm__ __volatile__( \
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"1: lwz %0,0(%1)\n" \
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" eieio\n" \
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" li %0,0\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: li %0,-1\n" \
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" b 2b\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 1b,3b\n" \
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".text" \
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: "=r" (retval) : "r"(addr));
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return (retval);
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#endif
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return 0;
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}
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