upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
2.7 KiB
108 lines
2.7 KiB
/*
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* (C) Copyright 2005
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* STMicrolelctronics, <www.st.com>
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SHOW_BOOT_PROGRESS
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void show_boot_progress(int progress)
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{
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printf("%i\n", progress);
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}
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#endif
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
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gd->bd->bi_boot_params = 0x00000100;
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writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
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writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
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writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
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writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
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/* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
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writel(0x0000305b, REG_FSMC_BCR1);
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writel(0x00033f33, REG_FSMC_BTR1);
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/* Set up SMCS0 for OneNand: sram-like once again */
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writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
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writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
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icache_enable();
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return 0;
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}
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int board_late_init(void)
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{
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/* Set the two I2C gpio lines to be gpio high */
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nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
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nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
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nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
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/* Reset the I2C port expander, on GPIO77 */
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nmk_gpio_af(77, GPIO_GPIO);
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nmk_gpio_dir(77, 1);
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nmk_gpio_set(77, 0);
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udelay(10);
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nmk_gpio_set(77, 1);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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