upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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647 lines
15 KiB
647 lines
15 KiB
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* Portions of this file are derived from the Linux kernel source
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* Copyright (C) 1991, 1992 Linus Torvalds
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/interrupt.h>
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#define DECLARE_INTERRUPT(x) \
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".globl irq_"#x"\n" \
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".hidden irq_"#x"\n" \
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".type irq_"#x", @function\n" \
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"irq_"#x":\n" \
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"pushl $"#x"\n" \
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"jmp irq_common_entry\n"
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/*
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* Volatile isn't enough to prevent the compiler from reordering the
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* read/write functions for the control registers and messing everything up.
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* A memory clobber would solve the problem, but would prevent reordering of
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* all loads stores around it, which can hurt performance. Solution is to
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* use a variable and mimic reads and writes to it to enforce serialization
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*/
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static unsigned long __force_order;
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static inline unsigned long read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr4(void)
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{
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unsigned long val;
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asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val));
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break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val));
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break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val));
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break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val));
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break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val));
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break;
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case 7:
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asm("mov %%db7, %0" :"=r" (val));
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break;
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default:
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val = 0;
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}
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return val;
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}
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void dump_regs(struct pt_regs *regs)
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{
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unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
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unsigned long d0, d1, d2, d3, d6, d7;
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printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
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(u16)regs->xcs, regs->eip, regs->eflags);
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printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
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regs->eax, regs->ebx, regs->ecx, regs->edx);
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printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
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regs->esi, regs->edi, regs->ebp, regs->esp);
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printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
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(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
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cr0 = read_cr0();
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cr2 = read_cr2();
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cr3 = read_cr3();
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cr4 = read_cr4();
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printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
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cr0, cr2, cr3, cr4);
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d0 = get_debugreg(0);
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d1 = get_debugreg(1);
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d2 = get_debugreg(2);
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d3 = get_debugreg(3);
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printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
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d0, d1, d2, d3);
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d6 = get_debugreg(6);
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d7 = get_debugreg(7);
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printf("DR6: %08lx DR7: %08lx\n",
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d6, d7);
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}
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struct idt_entry {
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u16 base_low;
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u16 selector;
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u8 res;
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u8 access;
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u16 base_high;
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} __attribute__ ((packed));
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struct desc_ptr {
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unsigned short size;
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unsigned long address;
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unsigned short segment;
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} __attribute__((packed));
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struct idt_entry idt[256];
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struct desc_ptr idt_ptr;
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static inline void load_idt(const struct desc_ptr *dtr)
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{
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asm volatile("cs lidt %0"::"m" (*dtr));
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}
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void set_vector(u8 intnum, void *routine)
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{
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idt[intnum].base_high = (u16)((u32)(routine) >> 16);
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idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
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}
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void irq_0(void);
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void irq_1(void);
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int cpu_init_interrupts(void)
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{
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int i;
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int irq_entry_size = irq_1 - irq_0;
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void *irq_entry = (void *)irq_0;
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/* Just in case... */
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disable_interrupts();
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/* Setup the IDT */
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for (i=0;i<256;i++) {
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idt[i].access = 0x8e;
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idt[i].res = 0;
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idt[i].selector = 0x10;
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set_vector(i, irq_entry);
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irq_entry += irq_entry_size;
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}
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idt_ptr.size = 256 * 8;
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idt_ptr.address = (unsigned long) idt;
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idt_ptr.segment = 0x18;
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load_idt(&idt_ptr);
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/* It is now safe to enable interrupts */
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enable_interrupts();
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return 0;
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}
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void __do_irq(int irq)
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{
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printf("Unhandled IRQ : %d\n", irq);
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}
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void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
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void enable_interrupts(void)
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{
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asm("sti\n");
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}
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int disable_interrupts(void)
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{
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long flags;
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asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
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return (flags&0x200); /* IE flags is bit 9 */
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}
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/* IRQ Low-Level Service Routine */
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__isr__ irq_llsr(struct pt_regs *regs)
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{
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/*
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* For detailed description of each exception, refer to:
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* Intel® 64 and IA-32 Architectures Software Developer's Manual
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* Volume 1: Basic Architecture
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* Order Number: 253665-029US, November 2008
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* Table 6-1. Exceptions and Interrupts
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*/
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switch (regs->orig_eax) {
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case 0x00:
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printf("Divide Error (Division by zero)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x01:
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printf("Debug Interrupt (Single step)\n");
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dump_regs(regs);
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break;
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case 0x02:
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printf("NMI Interrupt\n");
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dump_regs(regs);
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break;
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case 0x03:
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printf("Breakpoint\n");
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dump_regs(regs);
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break;
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case 0x04:
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printf("Overflow\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x05:
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printf("BOUND Range Exceeded\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x06:
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printf("Invalid Opcode (UnDefined Opcode)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x07:
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printf("Device Not Available (No Math Coprocessor)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x08:
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printf("Double fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x09:
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printf("Co-processor segment overrun\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0a:
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printf("Invalid TSS\n");
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dump_regs(regs);
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break;
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case 0x0b:
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printf("Segment Not Present\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0c:
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printf("Stack Segment Fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0d:
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printf("General Protection\n");
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dump_regs(regs);
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break;
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case 0x0e:
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printf("Page fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0f:
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printf("Floating-Point Error (Math Fault)\n");
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dump_regs(regs);
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break;
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case 0x10:
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printf("Alignment check\n");
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dump_regs(regs);
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break;
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case 0x11:
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printf("Machine Check\n");
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dump_regs(regs);
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break;
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case 0x12:
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printf("SIMD Floating-Point Exception\n");
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dump_regs(regs);
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break;
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case 0x13:
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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case 0x18:
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case 0x19:
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case 0x1a:
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case 0x1b:
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case 0x1c:
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case 0x1d:
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case 0x1e:
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case 0x1f:
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printf("Reserved Exception\n");
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dump_regs(regs);
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break;
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default:
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/* Hardware or User IRQ */
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do_irq(regs->orig_eax);
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}
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}
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/*
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* OK - This looks really horrible, but it serves a purpose - It helps create
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* fully relocatable code.
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* - The call to irq_llsr will be a relative jump
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* - The IRQ entries will be guaranteed to be in order
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* Interrupt entries are now very small (a push and a jump) but they are
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* now slower (all registers pushed on stack which provides complete
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* crash dumps in the low level handlers
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*/
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asm(".globl irq_common_entry\n" \
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".hidden irq_common_entry\n" \
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".type irq_common_entry, @function\n" \
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"irq_common_entry:\n" \
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"cld\n" \
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"pushl %gs\n" \
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"pushl %fs\n" \
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"pushl %es\n" \
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"pushl %ds\n" \
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"pushl %eax\n" \
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"pushl %ebp\n" \
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"pushl %edi\n" \
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"pushl %esi\n" \
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"pushl %edx\n" \
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"pushl %ecx\n" \
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"pushl %ebx\n" \
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"mov %esp, %eax\n" \
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"pushl %ebp\n" \
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"movl %esp,%ebp\n" \
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"pushl %eax\n" \
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"call irq_llsr\n" \
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"popl %eax\n" \
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"leave\n"\
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"popl %ebx\n" \
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"popl %ecx\n" \
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"popl %edx\n" \
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"popl %esi\n" \
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"popl %edi\n" \
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"popl %ebp\n" \
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"popl %eax\n" \
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"popl %ds\n" \
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"popl %es\n" \
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"popl %fs\n" \
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"popl %gs\n" \
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"add $4, %esp\n" \
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"iret\n" \
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DECLARE_INTERRUPT(0) \
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DECLARE_INTERRUPT(1) \
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DECLARE_INTERRUPT(2) \
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DECLARE_INTERRUPT(3) \
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DECLARE_INTERRUPT(4) \
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DECLARE_INTERRUPT(5) \
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DECLARE_INTERRUPT(6) \
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DECLARE_INTERRUPT(7) \
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DECLARE_INTERRUPT(8) \
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DECLARE_INTERRUPT(9) \
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DECLARE_INTERRUPT(10) \
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DECLARE_INTERRUPT(11) \
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DECLARE_INTERRUPT(12) \
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DECLARE_INTERRUPT(13) \
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DECLARE_INTERRUPT(14) \
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DECLARE_INTERRUPT(15) \
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DECLARE_INTERRUPT(16) \
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DECLARE_INTERRUPT(17) \
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DECLARE_INTERRUPT(18) \
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DECLARE_INTERRUPT(19) \
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DECLARE_INTERRUPT(20) \
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DECLARE_INTERRUPT(21) \
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DECLARE_INTERRUPT(22) \
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DECLARE_INTERRUPT(23) \
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DECLARE_INTERRUPT(24) \
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DECLARE_INTERRUPT(25) \
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DECLARE_INTERRUPT(26) \
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DECLARE_INTERRUPT(27) \
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DECLARE_INTERRUPT(28) \
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DECLARE_INTERRUPT(29) \
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DECLARE_INTERRUPT(30) \
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DECLARE_INTERRUPT(31) \
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DECLARE_INTERRUPT(32) \
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DECLARE_INTERRUPT(33) \
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DECLARE_INTERRUPT(34) \
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DECLARE_INTERRUPT(35) \
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DECLARE_INTERRUPT(36) \
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DECLARE_INTERRUPT(37) \
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DECLARE_INTERRUPT(38) \
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DECLARE_INTERRUPT(39) \
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|
DECLARE_INTERRUPT(40) \
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|
DECLARE_INTERRUPT(41) \
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|
DECLARE_INTERRUPT(42) \
|
|
DECLARE_INTERRUPT(43) \
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|
DECLARE_INTERRUPT(44) \
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|
DECLARE_INTERRUPT(45) \
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|
DECLARE_INTERRUPT(46) \
|
|
DECLARE_INTERRUPT(47) \
|
|
DECLARE_INTERRUPT(48) \
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|
DECLARE_INTERRUPT(49) \
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|
DECLARE_INTERRUPT(50) \
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|
DECLARE_INTERRUPT(51) \
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|
DECLARE_INTERRUPT(52) \
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|
DECLARE_INTERRUPT(53) \
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|
DECLARE_INTERRUPT(54) \
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|
DECLARE_INTERRUPT(55) \
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|
DECLARE_INTERRUPT(56) \
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|
DECLARE_INTERRUPT(57) \
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|
DECLARE_INTERRUPT(58) \
|
|
DECLARE_INTERRUPT(59) \
|
|
DECLARE_INTERRUPT(60) \
|
|
DECLARE_INTERRUPT(61) \
|
|
DECLARE_INTERRUPT(62) \
|
|
DECLARE_INTERRUPT(63) \
|
|
DECLARE_INTERRUPT(64) \
|
|
DECLARE_INTERRUPT(65) \
|
|
DECLARE_INTERRUPT(66) \
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|
DECLARE_INTERRUPT(67) \
|
|
DECLARE_INTERRUPT(68) \
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|
DECLARE_INTERRUPT(69) \
|
|
DECLARE_INTERRUPT(70) \
|
|
DECLARE_INTERRUPT(71) \
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|
DECLARE_INTERRUPT(72) \
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|
DECLARE_INTERRUPT(73) \
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|
DECLARE_INTERRUPT(74) \
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|
DECLARE_INTERRUPT(75) \
|
|
DECLARE_INTERRUPT(76) \
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|
DECLARE_INTERRUPT(77) \
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|
DECLARE_INTERRUPT(78) \
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|
DECLARE_INTERRUPT(79) \
|
|
DECLARE_INTERRUPT(80) \
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|
DECLARE_INTERRUPT(81) \
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|
DECLARE_INTERRUPT(82) \
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|
DECLARE_INTERRUPT(83) \
|
|
DECLARE_INTERRUPT(84) \
|
|
DECLARE_INTERRUPT(85) \
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|
DECLARE_INTERRUPT(86) \
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|
DECLARE_INTERRUPT(87) \
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|
DECLARE_INTERRUPT(88) \
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|
DECLARE_INTERRUPT(89) \
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|
DECLARE_INTERRUPT(90) \
|
|
DECLARE_INTERRUPT(91) \
|
|
DECLARE_INTERRUPT(92) \
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|
DECLARE_INTERRUPT(93) \
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|
DECLARE_INTERRUPT(94) \
|
|
DECLARE_INTERRUPT(95) \
|
|
DECLARE_INTERRUPT(97) \
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|
DECLARE_INTERRUPT(96) \
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|
DECLARE_INTERRUPT(98) \
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|
DECLARE_INTERRUPT(99) \
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|
DECLARE_INTERRUPT(100) \
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|
DECLARE_INTERRUPT(101) \
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|
DECLARE_INTERRUPT(102) \
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DECLARE_INTERRUPT(103) \
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DECLARE_INTERRUPT(104) \
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DECLARE_INTERRUPT(105) \
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|
DECLARE_INTERRUPT(106) \
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|
DECLARE_INTERRUPT(107) \
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|
DECLARE_INTERRUPT(108) \
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|
DECLARE_INTERRUPT(109) \
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|
DECLARE_INTERRUPT(110) \
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|
DECLARE_INTERRUPT(111) \
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|
DECLARE_INTERRUPT(112) \
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|
DECLARE_INTERRUPT(113) \
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|
DECLARE_INTERRUPT(114) \
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|
DECLARE_INTERRUPT(115) \
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|
DECLARE_INTERRUPT(116) \
|
|
DECLARE_INTERRUPT(117) \
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|
DECLARE_INTERRUPT(118) \
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|
DECLARE_INTERRUPT(119) \
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|
DECLARE_INTERRUPT(120) \
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DECLARE_INTERRUPT(121) \
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DECLARE_INTERRUPT(122) \
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DECLARE_INTERRUPT(123) \
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|
DECLARE_INTERRUPT(124) \
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DECLARE_INTERRUPT(125) \
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DECLARE_INTERRUPT(126) \
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|
DECLARE_INTERRUPT(127) \
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|
DECLARE_INTERRUPT(128) \
|
|
DECLARE_INTERRUPT(129) \
|
|
DECLARE_INTERRUPT(130) \
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DECLARE_INTERRUPT(131) \
|
|
DECLARE_INTERRUPT(132) \
|
|
DECLARE_INTERRUPT(133) \
|
|
DECLARE_INTERRUPT(134) \
|
|
DECLARE_INTERRUPT(135) \
|
|
DECLARE_INTERRUPT(136) \
|
|
DECLARE_INTERRUPT(137) \
|
|
DECLARE_INTERRUPT(138) \
|
|
DECLARE_INTERRUPT(139) \
|
|
DECLARE_INTERRUPT(140) \
|
|
DECLARE_INTERRUPT(141) \
|
|
DECLARE_INTERRUPT(142) \
|
|
DECLARE_INTERRUPT(143) \
|
|
DECLARE_INTERRUPT(144) \
|
|
DECLARE_INTERRUPT(145) \
|
|
DECLARE_INTERRUPT(146) \
|
|
DECLARE_INTERRUPT(147) \
|
|
DECLARE_INTERRUPT(148) \
|
|
DECLARE_INTERRUPT(149) \
|
|
DECLARE_INTERRUPT(150) \
|
|
DECLARE_INTERRUPT(151) \
|
|
DECLARE_INTERRUPT(152) \
|
|
DECLARE_INTERRUPT(153) \
|
|
DECLARE_INTERRUPT(154) \
|
|
DECLARE_INTERRUPT(155) \
|
|
DECLARE_INTERRUPT(156) \
|
|
DECLARE_INTERRUPT(157) \
|
|
DECLARE_INTERRUPT(158) \
|
|
DECLARE_INTERRUPT(159) \
|
|
DECLARE_INTERRUPT(160) \
|
|
DECLARE_INTERRUPT(161) \
|
|
DECLARE_INTERRUPT(162) \
|
|
DECLARE_INTERRUPT(163) \
|
|
DECLARE_INTERRUPT(164) \
|
|
DECLARE_INTERRUPT(165) \
|
|
DECLARE_INTERRUPT(166) \
|
|
DECLARE_INTERRUPT(167) \
|
|
DECLARE_INTERRUPT(168) \
|
|
DECLARE_INTERRUPT(169) \
|
|
DECLARE_INTERRUPT(170) \
|
|
DECLARE_INTERRUPT(171) \
|
|
DECLARE_INTERRUPT(172) \
|
|
DECLARE_INTERRUPT(173) \
|
|
DECLARE_INTERRUPT(174) \
|
|
DECLARE_INTERRUPT(175) \
|
|
DECLARE_INTERRUPT(176) \
|
|
DECLARE_INTERRUPT(177) \
|
|
DECLARE_INTERRUPT(178) \
|
|
DECLARE_INTERRUPT(179) \
|
|
DECLARE_INTERRUPT(180) \
|
|
DECLARE_INTERRUPT(181) \
|
|
DECLARE_INTERRUPT(182) \
|
|
DECLARE_INTERRUPT(183) \
|
|
DECLARE_INTERRUPT(184) \
|
|
DECLARE_INTERRUPT(185) \
|
|
DECLARE_INTERRUPT(186) \
|
|
DECLARE_INTERRUPT(187) \
|
|
DECLARE_INTERRUPT(188) \
|
|
DECLARE_INTERRUPT(189) \
|
|
DECLARE_INTERRUPT(190) \
|
|
DECLARE_INTERRUPT(191) \
|
|
DECLARE_INTERRUPT(192) \
|
|
DECLARE_INTERRUPT(193) \
|
|
DECLARE_INTERRUPT(194) \
|
|
DECLARE_INTERRUPT(195) \
|
|
DECLARE_INTERRUPT(196) \
|
|
DECLARE_INTERRUPT(197) \
|
|
DECLARE_INTERRUPT(198) \
|
|
DECLARE_INTERRUPT(199) \
|
|
DECLARE_INTERRUPT(200) \
|
|
DECLARE_INTERRUPT(201) \
|
|
DECLARE_INTERRUPT(202) \
|
|
DECLARE_INTERRUPT(203) \
|
|
DECLARE_INTERRUPT(204) \
|
|
DECLARE_INTERRUPT(205) \
|
|
DECLARE_INTERRUPT(206) \
|
|
DECLARE_INTERRUPT(207) \
|
|
DECLARE_INTERRUPT(208) \
|
|
DECLARE_INTERRUPT(209) \
|
|
DECLARE_INTERRUPT(210) \
|
|
DECLARE_INTERRUPT(211) \
|
|
DECLARE_INTERRUPT(212) \
|
|
DECLARE_INTERRUPT(213) \
|
|
DECLARE_INTERRUPT(214) \
|
|
DECLARE_INTERRUPT(215) \
|
|
DECLARE_INTERRUPT(216) \
|
|
DECLARE_INTERRUPT(217) \
|
|
DECLARE_INTERRUPT(218) \
|
|
DECLARE_INTERRUPT(219) \
|
|
DECLARE_INTERRUPT(220) \
|
|
DECLARE_INTERRUPT(221) \
|
|
DECLARE_INTERRUPT(222) \
|
|
DECLARE_INTERRUPT(223) \
|
|
DECLARE_INTERRUPT(224) \
|
|
DECLARE_INTERRUPT(225) \
|
|
DECLARE_INTERRUPT(226) \
|
|
DECLARE_INTERRUPT(227) \
|
|
DECLARE_INTERRUPT(228) \
|
|
DECLARE_INTERRUPT(229) \
|
|
DECLARE_INTERRUPT(230) \
|
|
DECLARE_INTERRUPT(231) \
|
|
DECLARE_INTERRUPT(232) \
|
|
DECLARE_INTERRUPT(233) \
|
|
DECLARE_INTERRUPT(234) \
|
|
DECLARE_INTERRUPT(235) \
|
|
DECLARE_INTERRUPT(236) \
|
|
DECLARE_INTERRUPT(237) \
|
|
DECLARE_INTERRUPT(238) \
|
|
DECLARE_INTERRUPT(239) \
|
|
DECLARE_INTERRUPT(240) \
|
|
DECLARE_INTERRUPT(241) \
|
|
DECLARE_INTERRUPT(242) \
|
|
DECLARE_INTERRUPT(243) \
|
|
DECLARE_INTERRUPT(244) \
|
|
DECLARE_INTERRUPT(245) \
|
|
DECLARE_INTERRUPT(246) \
|
|
DECLARE_INTERRUPT(247) \
|
|
DECLARE_INTERRUPT(248) \
|
|
DECLARE_INTERRUPT(249) \
|
|
DECLARE_INTERRUPT(250) \
|
|
DECLARE_INTERRUPT(251) \
|
|
DECLARE_INTERRUPT(252) \
|
|
DECLARE_INTERRUPT(253) \
|
|
DECLARE_INTERRUPT(254) \
|
|
DECLARE_INTERRUPT(255));
|
|
|