upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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859 lines
24 KiB
859 lines
24 KiB
/***********************************************************************
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*
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* Copyright (C) 2005 by Videon Central, Inc.
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*
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* $Id$
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* @Author: Arthur Shipkowski
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* @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like
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* the older netarmeth driver. Note that attempting to filter
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* broadcast and multicast out in the SAFR register will cause
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* bad things due to released errata.
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* @References: [1] NS7520 Hardware Reference, December 2003
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* [2] Intel LXT971 Datasheet #249414 Rev. 02
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*
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***********************************************************************/
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#include <common.h>
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#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
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#include <net.h> /* NetSendPacket */
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#include <asm/arch/netarm_registers.h>
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#include <asm/arch/netarm_dma_module.h>
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#include "ns7520_eth.h" /* for Ethernet and PHY */
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/**
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* Send an error message to the terminal.
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*/
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#define ERROR(x) \
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do { \
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char *__foo = strrchr(__FILE__, '/'); \
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\
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printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
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__LINE__, __FUNCTION__); \
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printf x; printf("\n"); \
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} while (0);
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/* some definition to make transistion to linux easier */
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#define NS7520_DRIVER_NAME "eth"
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#define KERN_WARNING "Warning:"
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#define KERN_ERR "Error:"
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#define KERN_INFO "Info:"
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#if 1
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# define DEBUG
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#endif
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#ifdef DEBUG
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# define printk printf
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# define DEBUG_INIT 0x0001
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# define DEBUG_MINOR 0x0002
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# define DEBUG_RX 0x0004
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# define DEBUG_TX 0x0008
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# define DEBUG_INT 0x0010
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# define DEBUG_POLL 0x0020
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# define DEBUG_LINK 0x0040
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# define DEBUG_MII 0x0100
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# define DEBUG_MII_LOW 0x0200
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# define DEBUG_MEM 0x0400
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# define DEBUG_ERROR 0x4000
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# define DEBUG_ERROR_CRIT 0x8000
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static int nDebugLvl = DEBUG_ERROR_CRIT;
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# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
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printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
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# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
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printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
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# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
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printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
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# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
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printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
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# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
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printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
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# define ASSERT( expr, func ) if( !( expr ) ) { \
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printf( "Assertion failed! %s:line %d %s\n", \
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(int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
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func }
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#else /* DEBUG */
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# define printk(...)
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# define DEBUG_ARGS0( FLG, a0 )
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# define DEBUG_ARGS1( FLG, a0, a1 )
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# define DEBUG_ARGS2( FLG, a0, a1, a2 )
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# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
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# define DEBUG_FN( n )
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# define ASSERT(expr, func)
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#endif /* DEBUG */
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#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */
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#define TX_TIMEOUT (5*CFG_HZ) /* in s */
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#define RX_STALL_WORKAROUND_CNT 100
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static int ns7520_eth_reset(void);
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static void ns7520_link_auto_negotiate(void);
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static void ns7520_link_update_egcr(void);
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static void ns7520_link_print_changed(void);
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/* the PHY stuff */
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static char ns7520_mii_identify_phy(void);
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static unsigned short ns7520_mii_read(unsigned short uiRegister);
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static void ns7520_mii_write(unsigned short uiRegister,
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unsigned short uiData);
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static unsigned int ns7520_mii_get_clock_divisor(unsigned int
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unMaxMDIOClk);
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static unsigned int ns7520_mii_poll_busy(void);
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static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
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static unsigned int uiLastLinkStatus;
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static PhyType phyDetected = PHY_NONE;
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/***********************************************************************
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* @Function: eth_init
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* @Return: -1 on failure otherwise 0
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* @Descr: Initializes the ethernet engine and uses either FS Forth's default
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* MAC addr or the one in environment
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***********************************************************************/
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int eth_init(bd_t * pbis)
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{
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unsigned char aucMACAddr[6];
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char *pcTmp = getenv("ethaddr");
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char *pcEnd;
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int i;
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DEBUG_FN(DEBUG_INIT);
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/* no need to check for hardware */
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if (!ns7520_eth_reset())
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return -1;
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if (NULL == pcTmp)
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return -1;
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for (i = 0; i < 6; i++) {
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aucMACAddr[i] =
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pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0;
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pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
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}
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/* configure ethernet address */
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*get_eth_reg_addr(NS7520_ETH_SA1) =
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aucMACAddr[5] << 8 | aucMACAddr[4];
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*get_eth_reg_addr(NS7520_ETH_SA2) =
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aucMACAddr[3] << 8 | aucMACAddr[2];
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*get_eth_reg_addr(NS7520_ETH_SA3) =
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aucMACAddr[1] << 8 | aucMACAddr[0];
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/* enable hardware */
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*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
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*get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
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*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
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/* the linux kernel may give packets < 60 bytes, for example arp */
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*get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
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NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
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/* Broadcast/multicast allowed; if you don't set this even unicast chokes */
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/* Based on NS7520 errata documentation */
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*get_eth_reg_addr(NS7520_ETH_SAFR) =
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NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
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/* enable receive and transmit FIFO, use 10/100 Mbps MII */
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*get_eth_reg_addr(NS7520_ETH_EGCR) |=
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NS7520_ETH_EGCR_ETXWM_75 |
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NS7520_ETH_EGCR_ERX |
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NS7520_ETH_EGCR_ERXREG |
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NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX;
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return 0;
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}
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/***********************************************************************
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* @Function: eth_send
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* @Return: -1 on timeout otherwise 1
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* @Descr: sends one frame by DMA
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***********************************************************************/
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int eth_send(volatile void *pPacket, int nLen)
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{
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int i, length32, retval = 1;
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char *pa;
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unsigned int *pa32, lastp = 0, rest;
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unsigned int status;
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pa = (char *) pPacket;
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pa32 = (unsigned int *) pPacket;
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length32 = nLen / 4;
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rest = nLen % 4;
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/* make sure there's no garbage in the last word */
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switch (rest) {
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case 0:
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lastp = pa32[length32 - 1];
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length32--;
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break;
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case 1:
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lastp = pa32[length32] & 0x000000ff;
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break;
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case 2:
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lastp = pa32[length32] & 0x0000ffff;
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break;
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case 3:
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lastp = pa32[length32] & 0x00ffffff;
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break;
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}
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while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
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NS7520_ETH_EGSR_TXREGE)
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== 0) {
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}
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/* write to the fifo */
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for (i = 0; i < length32; i++)
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*get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
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/* the last word is written to an extra register, this
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starts the transmission */
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*get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
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/* Wait for it to be done */
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while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
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== 0) {
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}
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status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
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*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */
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if (status & NS7520_ETH_ETSR_TXOK) {
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retval = 0; /* We're OK! */
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} else if (status & NS7520_ETH_ETSR_TXDEF) {
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printf("Deferred, we'll see.\n");
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retval = 0;
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} else if (status & NS7520_ETH_ETSR_TXAL) {
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printf("Late collision error, %d collisions.\n",
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(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
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NS7520_ETH_ETSR_TXCOLC);
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} else if (status & NS7520_ETH_ETSR_TXAEC) {
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printf("Excessive collisions: %d\n",
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(*get_eth_reg_addr(NS7520_ETH_ETSR)) &
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NS7520_ETH_ETSR_TXCOLC);
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} else if (status & NS7520_ETH_ETSR_TXAED) {
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printf("Excessive deferral on xmit.\n");
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} else if (status & NS7520_ETH_ETSR_TXAUR) {
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printf("Packet underrun.\n");
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} else if (status & NS7520_ETH_ETSR_TXAJ) {
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printf("Jumbo packet error.\n");
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} else {
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printf("Error: Should never get here.\n");
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}
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return (retval);
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}
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/***********************************************************************
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* @Function: eth_rx
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* @Return: size of last frame in bytes or 0 if no frame available
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* @Descr: gives one frame to U-Boot which has been copied by DMA engine already
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* to NetRxPackets[ 0 ].
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***********************************************************************/
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int eth_rx(void)
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{
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int i;
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unsigned short rxlen;
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unsigned short totrxlen = 0;
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unsigned int *addr;
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unsigned int rxstatus, lastrxlen;
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char *pa;
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/* If RXBR is 1, data block was received */
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while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
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NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
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/* get status register and the length of received block */
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rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
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rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
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/* clear RXBR to make fifo available */
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*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
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if (rxstatus & NS7520_ETH_ERSR_ROVER) {
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printf("Receive overrun, resetting FIFO.\n");
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*get_eth_reg_addr(NS7520_ETH_EGCR) &=
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~NS7520_ETH_EGCR_ERX;
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udelay(20);
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*get_eth_reg_addr(NS7520_ETH_EGCR) |=
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NS7520_ETH_EGCR_ERX;
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}
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if (rxlen == 0) {
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printf("Nothing.\n");
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return 0;
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}
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addr = (unsigned int *) NetRxPackets[0];
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pa = (char *) NetRxPackets[0];
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/* read the fifo */
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for (i = 0; i < rxlen / 4; i++) {
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*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
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addr++;
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}
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if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
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NS7520_ETH_EGSR_RXREGR) {
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/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
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lastrxlen =
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((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
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NS7520_ETH_EGSR_RXFDB_MA) >> 28;
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*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
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switch (lastrxlen) {
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case 1:
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*addr &= 0xff000000;
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break;
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case 2:
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*addr &= 0xffff0000;
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break;
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case 3:
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*addr &= 0xffffff00;
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break;
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}
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}
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/* Pass the packet up to the protocol layers. */
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NetReceive(NetRxPackets[0], rxlen - 4);
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totrxlen += rxlen - 4;
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}
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return totrxlen;
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}
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/***********************************************************************
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* @Function: eth_halt
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* @Return: n/a
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* @Descr: stops the ethernet engine
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***********************************************************************/
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void eth_halt(void)
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{
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DEBUG_FN(DEBUG_INIT);
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*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
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*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
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NS7520_ETH_EGCR_ERXDMA |
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NS7520_ETH_EGCR_ERXREG |
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NS7520_ETH_EGCR_ERXBR |
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NS7520_ETH_EGCR_ETX |
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NS7520_ETH_EGCR_ETXDMA);
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}
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/***********************************************************************
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* @Function: ns7520_eth_reset
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* @Return: 0 on failure otherwise 1
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* @Descr: resets the ethernet interface and the PHY,
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* performs auto negotiation or fixed modes
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***********************************************************************/
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static int ns7520_eth_reset(void)
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{
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DEBUG_FN(DEBUG_MINOR);
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/* Reset important registers */
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*get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */
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*get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
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*get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
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/* Reset MAC */
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*get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
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udelay(5);
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*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
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/* reset and initialize PHY */
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*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
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/* we don't support hot plugging of PHY, therefore we don't reset
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phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
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incorrect the first open
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may detect the PHY correctly but succeding will fail
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For reseting the PHY and identifying we have to use the standard
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MDIO CLOCK value 2.5 MHz only after hardware reset
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After having identified the PHY we will do faster */
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*get_eth_reg_addr(NS7520_ETH_MCFG) =
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ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
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/* reset PHY */
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ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET);
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ns7520_mii_write(PHY_COMMON_CTRL, 0);
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udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */
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/* MII clock has been setup to default, ns7520_mii_identify_phy should
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work for all */
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if (!ns7520_mii_identify_phy()) {
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printk(KERN_ERR NS7520_DRIVER_NAME
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": Unsupported PHY, aborting\n");
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return 0;
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}
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/* now take the highest MDIO clock possible after detection */
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*get_eth_reg_addr(NS7520_ETH_MCFG) =
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ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
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/* PHY has been detected, so there can be no abort reason and we can
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finish initializing ethernet */
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uiLastLinkStatus = 0xff; /* undefined */
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ns7520_link_auto_negotiate();
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if (phyDetected == PHY_LXT971A)
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/* set LED2 to link mode */
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ns7520_mii_write(PHY_LXT971_LED_CFG,
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(PHY_LXT971_LED_CFG_LINK_ACT <<
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PHY_LXT971_LED_CFG_SHIFT_LED2) |
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(PHY_LXT971_LED_CFG_TRANSMIT <<
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PHY_LXT971_LED_CFG_SHIFT_LED1));
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return 1;
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}
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/***********************************************************************
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* @Function: ns7520_link_auto_negotiate
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* @Return: void
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* @Descr: performs auto-negotation of link.
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***********************************************************************/
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static void ns7520_link_auto_negotiate(void)
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{
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unsigned long ulStartJiffies;
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unsigned short uiStatus;
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DEBUG_FN(DEBUG_LINK);
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/* run auto-negotation */
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/* define what we are capable of */
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ns7520_mii_write(PHY_COMMON_AUTO_ADV,
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PHY_COMMON_AUTO_ADV_100BTXFD |
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PHY_COMMON_AUTO_ADV_100BTX |
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PHY_COMMON_AUTO_ADV_10BTFD |
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PHY_COMMON_AUTO_ADV_10BT |
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PHY_COMMON_AUTO_ADV_802_3);
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/* start auto-negotiation */
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ns7520_mii_write(PHY_COMMON_CTRL,
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PHY_COMMON_CTRL_AUTO_NEG |
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PHY_COMMON_CTRL_RES_AUTO);
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/* wait for completion */
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ulStartJiffies = get_timer(0);
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while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
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uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
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if ((uiStatus &
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(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT))
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==
|
|
(PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) {
|
|
/* lucky we are, auto-negotiation succeeded */
|
|
ns7520_link_print_changed();
|
|
ns7520_link_update_egcr();
|
|
return;
|
|
}
|
|
}
|
|
|
|
DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n");
|
|
/* ignore invalid link settings */
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_link_update_egcr
|
|
* @Return: void
|
|
* @Descr: updates the EGCR and MAC2 link status after mode change or
|
|
* auto-negotation
|
|
***********************************************************************/
|
|
|
|
static void ns7520_link_update_egcr(void)
|
|
{
|
|
unsigned int unEGCR;
|
|
unsigned int unMAC2;
|
|
unsigned int unIPGT;
|
|
|
|
DEBUG_FN(DEBUG_LINK);
|
|
|
|
unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
|
|
unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
|
|
unIPGT =
|
|
*get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
|
|
|
|
unEGCR &= ~NS7520_ETH_EGCR_EFULLD;
|
|
unMAC2 &= ~NS7520_ETH_MAC2_FULLD;
|
|
if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
|
|
== PHY_LXT971_STAT2_DUPLEX_MODE) {
|
|
unEGCR |= NS7520_ETH_EGCR_EFULLD;
|
|
unMAC2 |= NS7520_ETH_MAC2_FULLD;
|
|
unIPGT |= 0x15; /* see [1] p. 167 */
|
|
} else
|
|
unIPGT |= 0x12; /* see [1] p. 167 */
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
|
|
*get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
|
|
*get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_link_print_changed
|
|
* @Return: void
|
|
* @Descr: checks whether the link status has changed and if so prints
|
|
* the new mode
|
|
***********************************************************************/
|
|
|
|
static void ns7520_link_print_changed(void)
|
|
{
|
|
unsigned short uiStatus;
|
|
unsigned short uiControl;
|
|
|
|
DEBUG_FN(DEBUG_LINK);
|
|
|
|
uiControl = ns7520_mii_read(PHY_COMMON_CTRL);
|
|
|
|
if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) ==
|
|
PHY_COMMON_CTRL_AUTO_NEG) {
|
|
/* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */
|
|
uiStatus = ns7520_mii_read(PHY_COMMON_STAT);
|
|
|
|
if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) {
|
|
printk(KERN_WARNING NS7520_DRIVER_NAME
|
|
": link down\n");
|
|
/* @TODO Linux: carrier_off */
|
|
} else {
|
|
/* @TODO Linux: carrier_on */
|
|
if (phyDetected == PHY_LXT971A) {
|
|
uiStatus =
|
|
ns7520_mii_read(PHY_LXT971_STAT2);
|
|
uiStatus &=
|
|
(PHY_LXT971_STAT2_100BTX |
|
|
PHY_LXT971_STAT2_DUPLEX_MODE |
|
|
PHY_LXT971_STAT2_AUTO_NEG);
|
|
|
|
/* mask out all uninteresting parts */
|
|
}
|
|
/* other PHYs must store there link information in
|
|
uiStatus as PHY_LXT971 */
|
|
}
|
|
} else {
|
|
/* mode has been forced, so uiStatus should be the same as the
|
|
last link status, enforce printing */
|
|
uiStatus = uiLastLinkStatus;
|
|
uiLastLinkStatus = 0xff;
|
|
}
|
|
|
|
if (uiStatus != uiLastLinkStatus) {
|
|
/* save current link status */
|
|
uiLastLinkStatus = uiStatus;
|
|
|
|
/* print new link status */
|
|
|
|
printk(KERN_INFO NS7520_DRIVER_NAME
|
|
": link mode %i Mbps %s duplex %s\n",
|
|
(uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
|
|
(uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
|
|
"half",
|
|
(uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
|
|
"");
|
|
}
|
|
}
|
|
|
|
/***********************************************************************
|
|
* the MII low level stuff
|
|
***********************************************************************/
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_mii_identify_phy
|
|
* @Return: 1 if supported PHY has been detected otherwise 0
|
|
* @Descr: checks for supported PHY and prints the IDs.
|
|
***********************************************************************/
|
|
|
|
static char ns7520_mii_identify_phy(void)
|
|
{
|
|
unsigned short uiID1;
|
|
unsigned short uiID2;
|
|
unsigned char *szName;
|
|
char cRes = 0;
|
|
|
|
DEBUG_FN(DEBUG_MII);
|
|
|
|
phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1);
|
|
|
|
switch (phyDetected) {
|
|
case PHY_LXT971A:
|
|
szName = "LXT971A";
|
|
uiID2 = ns7520_mii_read(PHY_COMMON_ID2);
|
|
nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
|
|
cRes = 1;
|
|
break;
|
|
case PHY_NONE:
|
|
default:
|
|
/* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
|
|
address or reset sets the wrong NS7520_ETH_MCFG_CLKS */
|
|
|
|
uiID2 = 0;
|
|
szName = "unknown";
|
|
nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
|
|
phyDetected = PHY_NONE;
|
|
}
|
|
|
|
printk(KERN_INFO NS7520_DRIVER_NAME
|
|
": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
|
|
|
|
return cRes;
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_mii_read
|
|
* @Return: the data read from PHY register uiRegister
|
|
* @Descr: the data read may be invalid if timed out. If so, a message
|
|
* is printed but the invalid data is returned.
|
|
* The fixed device address is being used.
|
|
***********************************************************************/
|
|
|
|
static unsigned short ns7520_mii_read(unsigned short uiRegister)
|
|
{
|
|
DEBUG_FN(DEBUG_MII_LOW);
|
|
|
|
/* write MII register to be read */
|
|
*get_eth_reg_addr(NS7520_ETH_MADR) =
|
|
CONFIG_PHY_ADDR << 8 | uiRegister;
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
|
|
|
|
if (!ns7520_mii_poll_busy())
|
|
printk(KERN_WARNING NS7520_DRIVER_NAME
|
|
": MII still busy in read\n");
|
|
/* continue to read */
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
|
|
|
|
return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_mii_write
|
|
* @Return: nothing
|
|
* @Descr: writes the data to the PHY register. In case of a timeout,
|
|
* no special handling is performed but a message printed
|
|
* The fixed device address is being used.
|
|
***********************************************************************/
|
|
|
|
static void ns7520_mii_write(unsigned short uiRegister,
|
|
unsigned short uiData)
|
|
{
|
|
DEBUG_FN(DEBUG_MII_LOW);
|
|
|
|
/* write MII register to be written */
|
|
*get_eth_reg_addr(NS7520_ETH_MADR) =
|
|
CONFIG_PHY_ADDR << 8 | uiRegister;
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
|
|
|
|
if (!ns7520_mii_poll_busy()) {
|
|
printf(KERN_WARNING NS7520_DRIVER_NAME
|
|
": MII still busy in write\n");
|
|
}
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_mii_get_clock_divisor
|
|
* @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS
|
|
* @Descr: if no clock divisor can be calculated for the
|
|
* current SYSCLK and the maximum MDIO Clock, a warning is printed
|
|
* and the greatest divisor is taken
|
|
***********************************************************************/
|
|
|
|
static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk)
|
|
{
|
|
struct {
|
|
unsigned int unSysClkDivisor;
|
|
unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */
|
|
} PHYClockDivisors[] = {
|
|
{
|
|
4, NS7520_ETH_MCFG_CLKS_4}, {
|
|
6, NS7520_ETH_MCFG_CLKS_6}, {
|
|
8, NS7520_ETH_MCFG_CLKS_8}, {
|
|
10, NS7520_ETH_MCFG_CLKS_10}, {
|
|
14, NS7520_ETH_MCFG_CLKS_14}, {
|
|
20, NS7520_ETH_MCFG_CLKS_20}, {
|
|
28, NS7520_ETH_MCFG_CLKS_28}
|
|
};
|
|
|
|
int nIndexSysClkDiv;
|
|
int nArraySize =
|
|
sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]);
|
|
unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to
|
|
greatest div */
|
|
|
|
DEBUG_FN(DEBUG_INIT);
|
|
|
|
for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
|
|
nIndexSysClkDiv++) {
|
|
/* find first sysclock divisor that isn't higher than 2.5 MHz
|
|
clock */
|
|
if (NETARM_XTAL_FREQ /
|
|
PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
|
|
unMaxMDIOClk) {
|
|
unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
|
|
break;
|
|
}
|
|
}
|
|
|
|
DEBUG_ARGS2(DEBUG_INIT,
|
|
"Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
|
|
unClks, unMaxMDIOClk);
|
|
|
|
/* return greatest divisor */
|
|
return unClks;
|
|
}
|
|
|
|
/***********************************************************************
|
|
* @Function: ns7520_mii_poll_busy
|
|
* @Return: 0 if timed out otherwise the remaing timeout
|
|
* @Descr: waits until the MII has completed a command or it times out
|
|
* code may be interrupted by hard interrupts.
|
|
* It is not checked what happens on multiple actions when
|
|
* the first is still being busy and we timeout.
|
|
***********************************************************************/
|
|
|
|
static unsigned int ns7520_mii_poll_busy(void)
|
|
{
|
|
unsigned int unTimeout = 1000;
|
|
|
|
DEBUG_FN(DEBUG_MII_LOW);
|
|
|
|
while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
|
|
== NS7520_ETH_MIND_BUSY) && unTimeout)
|
|
unTimeout--;
|
|
|
|
return unTimeout;
|
|
}
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
* Net+ARM ethernet MII functionality.
|
|
*/
|
|
#if defined(CONFIG_MII)
|
|
|
|
/**
|
|
* Maximum MII address we support
|
|
*/
|
|
#define MII_ADDRESS_MAX (31)
|
|
|
|
/**
|
|
* Maximum MII register address we support
|
|
*/
|
|
#define MII_REGISTER_MAX (31)
|
|
|
|
/**
|
|
* Ethernet MII interface return values for public functions.
|
|
*/
|
|
enum mii_status {
|
|
MII_STATUS_SUCCESS = 0,
|
|
MII_STATUS_FAILURE = 1,
|
|
};
|
|
|
|
/**
|
|
* Read a 16-bit value from an MII register.
|
|
*/
|
|
extern int ns7520_miiphy_read(char *devname, unsigned char const addr,
|
|
unsigned char const reg, unsigned short *const value)
|
|
{
|
|
int ret = MII_STATUS_FAILURE;
|
|
|
|
/* Parameter checks */
|
|
if (addr > MII_ADDRESS_MAX) {
|
|
ERROR(("invalid addr, 0x%02X", addr));
|
|
goto miiphy_read_failed_0;
|
|
}
|
|
|
|
if (reg > MII_REGISTER_MAX) {
|
|
ERROR(("invalid reg, 0x%02X", reg));
|
|
goto miiphy_read_failed_0;
|
|
}
|
|
|
|
if (value == NULL) {
|
|
ERROR(("NULL value"));
|
|
goto miiphy_read_failed_0;
|
|
}
|
|
|
|
DEBUG_FN(DEBUG_MII_LOW);
|
|
|
|
/* write MII register to be read */
|
|
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
|
|
|
|
if (!ns7520_mii_poll_busy())
|
|
printk(KERN_WARNING NS7520_DRIVER_NAME
|
|
": MII still busy in read\n");
|
|
/* continue to read */
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
|
|
|
|
*value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
|
|
ret = MII_STATUS_SUCCESS;
|
|
/* Fall through */
|
|
|
|
miiphy_read_failed_0:
|
|
return (ret);
|
|
}
|
|
|
|
/**
|
|
* Write a 16-bit value to an MII register.
|
|
*/
|
|
extern int ns7520_miiphy_write(char *devname, unsigned char const addr,
|
|
unsigned char const reg, unsigned short const value)
|
|
{
|
|
int ret = MII_STATUS_FAILURE;
|
|
|
|
/* Parameter checks */
|
|
if (addr > MII_ADDRESS_MAX) {
|
|
ERROR(("invalid addr, 0x%02X", addr));
|
|
goto miiphy_write_failed_0;
|
|
}
|
|
|
|
if (reg > MII_REGISTER_MAX) {
|
|
ERROR(("invalid reg, 0x%02X", reg));
|
|
goto miiphy_write_failed_0;
|
|
}
|
|
|
|
/* write MII register to be written */
|
|
*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
|
|
|
|
*get_eth_reg_addr(NS7520_ETH_MWTD) = value;
|
|
|
|
if (!ns7520_mii_poll_busy()) {
|
|
printf(KERN_WARNING NS7520_DRIVER_NAME
|
|
": MII still busy in write\n");
|
|
}
|
|
|
|
ret = MII_STATUS_SUCCESS;
|
|
/* Fall through */
|
|
|
|
miiphy_write_failed_0:
|
|
return (ret);
|
|
}
|
|
#endif /* defined(CONFIG_MII) */
|
|
#endif /* CONFIG_DRIVER_NS7520_ETHERNET */
|
|
|
|
int ns7520_miiphy_initialize(bd_t *bis)
|
|
{
|
|
#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
|
|
#if defined(CONFIG_MII)
|
|
miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|
|
|