upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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253 lines
7.7 KiB
253 lines
7.7 KiB
/*
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* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
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*
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* Configuation settings for the TI OMAP NetStar board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/omap1510.h>
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP1510 1 /* which is in a 5910 */
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/* Input clock of PLL */
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#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
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#define CONFIG_XTAL_FREQ 12000000
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_MISC_INIT_R /* There is nothing to really init */
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#define BOARD_LATE_INIT /* but we flash the LEDs here */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CFG_DEVICE_NULLDEV 1 /* enable null device */
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#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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/*
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* FLASH organization
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*/
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MAX_FLASH_BANKS 1
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#if (PHYS_SDRAM_1_SIZE == SZ_32M)
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/*#if 1*/
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#define CFG_FLASH_CFI /* Flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_MAX_FLASH_SECT 128
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#else
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#define PHYS_FLASH_1_SIZE SZ_1M
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#define CFG_MAX_FLASH_SECT 19
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#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
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#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
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#endif
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#define CFG_MONITOR_BASE PHYS_FLASH_1
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#define CFG_MONITOR_LEN SZ_256K
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH
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#define ENV_IS_SOLITARY
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#define CFG_ENV_ADDR 0x4000
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#define CFG_ENV_SIZE SZ_8K
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#define CFG_ENV_SECT_SIZE SZ_8K
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#define CFG_ENV_ADDR_REDUND 0x6000
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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#define CONFIG_ENV_OVERWRITE
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/*
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* Size of malloc() pool
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*/
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
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#define CFG_MALLOC_LEN SZ_4M
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/*
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* The stack size is set up in start.S using the settings below
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*/
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/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
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#define CONFIG_STACKSIZE SZ_1M /* regular stack */
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_SMC91111
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#define CONFIG_SMC91111_BASE 0x04000300
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/*
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE (-4)
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#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
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#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*#define CONFIG_SKIP_RELOCATE_UBOOT*/
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/*#define CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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* NAND flash
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*/
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE 0x04000000 + (2 << 23)
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/*
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* JFFS2 partitions (mtdparts command line support)
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*/
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
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#define CONFIG_LOOPW
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CFG_AUTOLOAD "n" /* No autoload */
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#define CONFIG_BOOTCOMMAND "run nboot"
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#define CONFIG_PREBOOT "run setup"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"setup=setenv bootargs console=ttyS0,$baudrate " \
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"$mtdparts\0" \
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"ospart=0\0" \
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"setpart=" \
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"if test -n $swapos; then " \
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"if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
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"setenv swapos; saveenv; " \
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"else " \
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"chpart nand0,$ospart; " \
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"fi\0" \
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"nfsargs=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
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"nfsroot=$rootpath root=/dev/nfs\0" \
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"flashargs=run setpart;setenv bootargs $bootargs " \
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"root=/dev/mtdblock$partition ro " \
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"rootfstype=jffs2\0" \
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"initrdargs=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
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"iboot=bootp;run initrdargs;tftp;bootm\0" \
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"fboot=run flashargs;fsload /boot/uImage;bootm\0" \
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"nboot=bootp;run nfsargs;tftp;bootm\0"
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#if 0 /* feel free to disable for development */
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#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
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#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
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#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
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#define CONFIG_BOOT_RETRY_TIME 30
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "# " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CONFIG_AUTO_COMPLETE
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#define CFG_MEMTEST_START PHYS_SDRAM_1
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#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
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/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
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* This time is further subdivided by a local divisor.
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*/
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#define CFG_TIMERBASE OMAP1510_TIMER1_BASE
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#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
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#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
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#define OMAP5910_DPLL_DIV 1
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#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
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(1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
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#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
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#define OMAP5910_LCD_DIV 2 /* CKL/4 */
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#define OMAP5910_ARM_DIV 0 /* CKL/1 */
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#define OMAP5910_DSP_DIV 0 /* CKL/1 */
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#define OMAP5910_TC_DIV 1 /* CKL/2 */
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#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
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#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
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#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
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#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
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(OMAP5910_LCD_DIV << 2) | \
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(OMAP5910_ARM_DIV << 4) | \
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(OMAP5910_DSP_DIV << 6) | \
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(OMAP5910_TC_DIV << 8) | \
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(OMAP5910_DSP_MMU_DIV << 10) | \
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(OMAP5910_ARM_TIM_SEL << 12))
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#endif /* __CONFIG_H */
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