upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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150 lines
3.8 KiB
150 lines
3.8 KiB
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/cache.h>
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volatile int *cf_icache_status = (int *)ICACHE_STATUS;
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volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
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void flush_cache(ulong start_addr, ulong size)
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{
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/* Must be implemented for all M68k processors with copy-back data cache */
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}
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int icache_status(void)
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{
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return *cf_icache_status;
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}
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int dcache_status(void)
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{
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return *cf_dcache_status;
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}
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void icache_enable(void)
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{
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icache_invalid();
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*cf_icache_status = 1;
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
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__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
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__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
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#else
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__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
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#endif
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__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
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}
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void icache_disable(void)
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{
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u32 temp = 0;
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*cf_icache_status = 0;
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icache_invalid();
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
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#else
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__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
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#endif
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}
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void icache_invalid(void)
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{
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u32 temp;
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temp = CONFIG_SYS_ICACHE_INV;
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if (*cf_icache_status)
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temp |= CONFIG_SYS_CACHE_ICACR;
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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}
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/*
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* data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
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* the dcache will be dummy in ColdFire V2 and V3
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*/
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void dcache_enable(void)
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{
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dcache_invalid();
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*cf_dcache_status = 1;
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
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__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
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#endif
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__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
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}
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void dcache_disable(void)
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{
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u32 temp = 0;
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*cf_dcache_status = 0;
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dcache_invalid();
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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#ifdef CONFIG_CF_V4
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__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
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#elif defined(CONFIG_CF_V4e)
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__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
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__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
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#endif
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}
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void dcache_invalid(void)
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{
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#ifdef CONFIG_CF_V4
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u32 temp;
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temp = CONFIG_SYS_DCACHE_INV;
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if (*cf_dcache_status)
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temp |= CONFIG_SYS_CACHE_DCACR;
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if (*cf_icache_status)
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temp |= CONFIG_SYS_CACHE_ICACR;
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__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
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#endif
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}
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